/* NO LONGER GENERATED -- sorry -- go ahead and edit. I got lazy. Feel free to fix buildregs.awk */
#include "i915_reg.h"
/* mask is unused. */
struct registers { char *name; int value; unsigned long mask; unsigned long extract, shift;};
struct registers struct_PRB1_TAIL[]={
	{NULL, 0},
};

struct registers struct_PRB1_HEAD[]={
	{NULL, 0},
};

struct registers struct_PRB1_START[]={
	{NULL, 0},
};

struct registers struct_PRB1_CTL[]={
	{NULL, 0},
};

struct registers struct_IPEIR_I965[]={
	{NULL, 0},
};

struct registers struct_IPEHR_I965[]={
	{NULL, 0},
};

struct registers struct_INSTDONE_I965[]={
	{NULL, 0},
};

struct registers struct_INSTPS[]={
	{NULL, 0},
};

struct registers struct_INSTDONE1[]={
	{NULL, 0},
};

struct registers struct_ACTHD_I965[]={
	{NULL, 0},
};

struct registers struct_HWS_PGA[]={
	{" HWS_START_ADDRESS_SHIFT ",HWS_START_ADDRESS_SHIFT },
	{" PWRCTX_EN ",PWRCTX_EN },
	{NULL, 0},
};

struct registers struct_IPEIR[]={
	{NULL, 0},
};

struct registers struct_IPEHR[]={
	{NULL, 0},
};

struct registers struct_INSTDONE[]={
	{NULL, 0},
};

struct registers struct_NOPID[]={
	{NULL, 0},
};

struct registers struct_HWSTAM[]={
	{NULL, 0},
};

struct registers struct_ERROR_GEN6[]={
	{NULL, 0},
};

struct registers struct__3D_CHICKEN[]={
	{NULL, 0},
};

struct registers struct__3D_CHICKEN2[]={
	{NULL, 0},
};

struct registers struct__3D_CHICKEN3[]={
	{NULL, 0},
};

struct registers struct_MI_MODE[]={
	{NULL, 0},
};

struct registers struct_GFX_MODE[]={
	{NULL, 0},
};

struct registers struct_GFX_MODE_GEN7[]={
	{" GFX_RUN_LIST_ENABLE ",GFX_RUN_LIST_ENABLE },
	{" GFX_TLB_INVALIDATE_ALWAYS ",GFX_TLB_INVALIDATE_ALWAYS },
	{" GFX_SURFACE_FAULT_ENABLE ",GFX_SURFACE_FAULT_ENABLE },
	{" GFX_REPLAY_MODE ",GFX_REPLAY_MODE },
	{" GFX_PSMI_GRANULARITY ",GFX_PSMI_GRANULARITY },
	{" GFX_PPGTT_ENABLE ",GFX_PPGTT_ENABLE },
	{NULL, 0},
};

struct registers struct_SCPD0[]={
	{NULL, 0},
};

struct registers struct_IER[]={
	{NULL, 0},
};

struct registers struct_IIR[]={
	{NULL, 0},
};

struct registers struct_IMR[]={
	{NULL, 0},
};

struct registers struct_ISR[]={
	{" I915_PIPE_CONTROL_NOTIFY_INTERRUPT ",I915_PIPE_CONTROL_NOTIFY_INTERRUPT },
	{" I915_DISPLAY_PORT_INTERRUPT ",I915_DISPLAY_PORT_INTERRUPT },
	{" I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT ",I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT },
	{" I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT ",I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT },
	{" I915_HWB_OOM_INTERRUPT ",I915_HWB_OOM_INTERRUPT },
	{" I915_SYNC_STATUS_INTERRUPT ",I915_SYNC_STATUS_INTERRUPT },
	{" I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT ",I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT },
	{" I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT ",I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT },
	{" I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT ",I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT },
	{" I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT ",I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT },
	{" I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT ",I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT },
	{" I915_DISPLAY_PIPE_A_EVENT_INTERRUPT ",I915_DISPLAY_PIPE_A_EVENT_INTERRUPT },
	{" I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT ",I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT },
	{" I915_DISPLAY_PIPE_B_EVENT_INTERRUPT ",I915_DISPLAY_PIPE_B_EVENT_INTERRUPT },
	{" I915_DEBUG_INTERRUPT ",I915_DEBUG_INTERRUPT },
	{" I915_USER_INTERRUPT ",I915_USER_INTERRUPT },
	{" I915_ASLE_INTERRUPT ",I915_ASLE_INTERRUPT },
	{" I915_BSD_USER_INTERRUPT ",I915_BSD_USER_INTERRUPT },
	{NULL, 0},
};

struct registers struct_EIR[]={
	{NULL, 0},
};

struct registers struct_EMR[]={
	{NULL, 0},
};

struct registers struct_ESR[]={
	{" GM45_ERROR_PAGE_TABLE ",GM45_ERROR_PAGE_TABLE },
	{" GM45_ERROR_MEM_PRIV ",GM45_ERROR_MEM_PRIV },
	{" I915_ERROR_PAGE_TABLE ",I915_ERROR_PAGE_TABLE },
	{" GM45_ERROR_CP_PRIV ",GM45_ERROR_CP_PRIV },
	{" I915_ERROR_MEMORY_REFRESH ",I915_ERROR_MEMORY_REFRESH },
	{" I915_ERROR_INSTRUCTION ",I915_ERROR_INSTRUCTION },
	{NULL, 0},
};

struct registers struct_INSTPM[]={
	{" INSTPM_FORCE_ORDERING ",INSTPM_FORCE_ORDERING },
	{NULL, 0},
};

struct registers struct_ACTHD[]={
	{NULL, 0},
};

struct registers struct_FW_BLC[]={
	{NULL, 0},
};

struct registers struct_FW_BLC2[]={
	{NULL, 0},
};

struct registers struct_FW_BLC_SELF[]={
	{" FW_BLC_SELF_EN_MASK ",FW_BLC_SELF_EN_MASK },
	{NULL, 0},
};

struct registers struct_MI_ARB_STATE[]={
	{" MI_ARB_RENDER_TLB_LOW_PRIORITY ",MI_ARB_RENDER_TLB_LOW_PRIORITY },
	{" MI_ARB_ISOCH_WAIT_GTT ",MI_ARB_ISOCH_WAIT_GTT },
	{" MI_ARB_BLOCK_GRANT_MASK ",MI_ARB_BLOCK_GRANT_MASK },
	{" MI_ARB_C3_LP_WRITE_ENABLE ",MI_ARB_C3_LP_WRITE_ENABLE },
	{" MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE ",MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE },
	{" MI_ARB_DUAL_DATA_PHASE_DISABLE ",MI_ARB_DUAL_DATA_PHASE_DISABLE },
	{" MI_ARB_CACHE_SNOOP_DISABLE ",MI_ARB_CACHE_SNOOP_DISABLE },
	{" MI_ARB_TIME_SLICE_MASK ",MI_ARB_TIME_SLICE_MASK },
	{" MI_ARB_TIME_SLICE_1 ",MI_ARB_TIME_SLICE_1 },
	{" MI_ARB_TIME_SLICE_2 ",MI_ARB_TIME_SLICE_2 },
	{" MI_ARB_TIME_SLICE_4 ",MI_ARB_TIME_SLICE_4 },
	{" MI_ARB_TIME_SLICE_6 ",MI_ARB_TIME_SLICE_6 },
	{" MI_ARB_TIME_SLICE_8 ",MI_ARB_TIME_SLICE_8 },
	{" MI_ARB_TIME_SLICE_10 ",MI_ARB_TIME_SLICE_10 },
	{" MI_ARB_TIME_SLICE_14 ",MI_ARB_TIME_SLICE_14 },
	{" MI_ARB_TIME_SLICE_16 ",MI_ARB_TIME_SLICE_16 },
	{" MI_ARB_LOW_PRIORITY_GRACE_4KB ",MI_ARB_LOW_PRIORITY_GRACE_4KB },
	{" MI_ARB_LOW_PRIORITY_GRACE_8KB ",MI_ARB_LOW_PRIORITY_GRACE_8KB },
	{" MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE ",MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE },
	{" MI_ARB_DISPLAY_PRIORITY_A_B ",MI_ARB_DISPLAY_PRIORITY_A_B },
	{" MI_ARB_DISPLAY_PRIORITY_B_A ",MI_ARB_DISPLAY_PRIORITY_B_A },
	{NULL, 0},
};


struct registers struct_BB_ADDR[]={
	{NULL, 0},
};

struct registers struct_GFX_FLSH_CNTL[]={
	{NULL, 0},
};

struct registers struct_ECOSKPD[]={
	{" ECO_GATING_CX_ONLY ",ECO_GATING_CX_ONLY },
	{" ECO_FLIP_DONE ",ECO_FLIP_DONE },
	{" GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT ",GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT },
	{" GEN6_RENDER_PPGTT_PAGE_FAULT ",GEN6_RENDER_PPGTT_PAGE_FAULT },
	{" GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED ",GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED },
	{" GEN6_RENDER_L3_PARITY_ERROR ",GEN6_RENDER_L3_PARITY_ERROR },
	{" GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT ",GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT },
	{" GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR ",GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR },
	{" GEN6_RENDER_SYNC_STATUS ",GEN6_RENDER_SYNC_STATUS },
	{" GEN6_RENDER_DEBUG_INTERRUPT ",GEN6_RENDER_DEBUG_INTERRUPT },
	{" GEN6_RENDER_USER_INTERRUPT ",GEN6_RENDER_USER_INTERRUPT },
	{NULL, 0},
};

struct registers struct_GEN6_BLITTER_HWSTAM[]={
	{NULL, 0},
};

struct registers struct_GEN6_BLITTER_IMR[]={
	{" GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT ",GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT },
	{" GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR ",GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR },
	{" GEN6_BLITTER_SYNC_STATUS ",GEN6_BLITTER_SYNC_STATUS },
	{" GEN6_BLITTER_USER_INTERRUPT ",GEN6_BLITTER_USER_INTERRUPT },
	{NULL, 0},
};

struct registers struct_GEN6_BLITTER_ECOSKPD[]={
	{" GEN6_BLITTER_LOCK_SHIFT ",GEN6_BLITTER_LOCK_SHIFT },
	{" GEN6_BLITTER_FBC_NOTIFY ",GEN6_BLITTER_FBC_NOTIFY },
	{NULL, 0},
};

struct registers struct_GEN6_BSD_HWSTAM[]={
	{NULL, 0},
};

struct registers struct_GEN6_BSD_IMR[]={
	{" GEN6_BSD_USER_INTERRUPT ",GEN6_BSD_USER_INTERRUPT },
	{NULL, 0},
};

struct registers struct_GEN6_BSD_RNCID[]={
	{NULL, 0},
};

struct registers struct_FBC_CFB_BASE[]={
	{NULL, 0},
};

struct registers struct_FBC_LL_BASE[]={
	{NULL, 0},
};

struct registers struct_FBC_CONTROL[]={
	{" FBC_CTL_EN ",FBC_CTL_EN },
	{" FBC_CTL_PERIODIC ",FBC_CTL_PERIODIC },
	{" FBC_CTL_INTERVAL_SHIFT ",FBC_CTL_INTERVAL_SHIFT },
	{" FBC_CTL_UNCOMPRESSIBLE ",FBC_CTL_UNCOMPRESSIBLE },
	{" FBC_CTL_C3_IDLE ",FBC_CTL_C3_IDLE },
	{" FBC_CTL_STRIDE_SHIFT ",FBC_CTL_STRIDE_SHIFT },
	{" FBC_CTL_FENCENO ",FBC_CTL_FENCENO },
	{NULL, 0},
};

struct registers struct_FBC_COMMAND[]={
	{" FBC_CMD_COMPRESS ",FBC_CMD_COMPRESS },
	{NULL, 0},
};

struct registers struct_FBC_STATUS[]={
	{" FBC_STAT_COMPRESSING ",FBC_STAT_COMPRESSING },
	{" FBC_STAT_COMPRESSED ",FBC_STAT_COMPRESSED },
	{" FBC_STAT_MODIFIED ",FBC_STAT_MODIFIED },
	{" FBC_STAT_CURRENT_LINE ",FBC_STAT_CURRENT_LINE },
	{NULL, 0},
};

struct registers struct_FBC_CONTROL2[]={
	{" FBC_CTL_FENCE_DBL ",FBC_CTL_FENCE_DBL },
	{" FBC_CTL_IDLE_IMM ",FBC_CTL_IDLE_IMM },
	{" FBC_CTL_IDLE_FULL ",FBC_CTL_IDLE_FULL },
	{" FBC_CTL_IDLE_LINE ",FBC_CTL_IDLE_LINE },
	{" FBC_CTL_IDLE_DEBUG ",FBC_CTL_IDLE_DEBUG },
	{" FBC_CTL_CPU_FENCE ",FBC_CTL_CPU_FENCE },
	{" FBC_CTL_PLANEA ",FBC_CTL_PLANEA },
	{" FBC_CTL_PLANEB ",FBC_CTL_PLANEB },
	{NULL, 0},
};

struct registers struct_FBC_FENCE_OFF[]={
	{NULL, 0},
};

struct registers struct_FBC_TAG[]={
	{" FBC_LL_SIZE ",FBC_LL_SIZE },
	{" DPFC_CTL_EN ",DPFC_CTL_EN },
	{" DPFC_CTL_PLANEA ",DPFC_CTL_PLANEA },
	{" DPFC_CTL_PLANEB ",DPFC_CTL_PLANEB },
	{" DPFC_CTL_FENCE_EN ",DPFC_CTL_FENCE_EN },
	{" DPFC_CTL_PERSISTENT_MODE ",DPFC_CTL_PERSISTENT_MODE },
	{" DPFC_SR_EN ",DPFC_SR_EN },
	{" DPFC_CTL_LIMIT_1X ",DPFC_CTL_LIMIT_1X },
	{" DPFC_CTL_LIMIT_2X ",DPFC_CTL_LIMIT_2X },
	{" DPFC_CTL_LIMIT_4X ",DPFC_CTL_LIMIT_4X },
	{" DPFC_RECOMP_STALL_EN ",DPFC_RECOMP_STALL_EN },
	{" DPFC_RECOMP_STALL_WM_SHIFT ",DPFC_RECOMP_STALL_WM_SHIFT },
	{" DPFC_RECOMP_TIMER_COUNT_SHIFT ",DPFC_RECOMP_TIMER_COUNT_SHIFT },
	{" DPFC_INVAL_SEG_SHIFT ",DPFC_INVAL_SEG_SHIFT },
	{" DPFC_COMP_SEG_SHIFT ",DPFC_COMP_SEG_SHIFT },
	{" DPFC_HT_MODIFY ",DPFC_HT_MODIFY },
	{NULL, 0},
};

struct registers struct_ILK_DPFC_CB_BASE[]={
	{NULL, 0},
};

struct registers struct_ILK_DPFC_CONTROL[]={
	{NULL, 0},
};

struct registers struct_ILK_DPFC_RECOMP_CTL[]={
	{NULL, 0},
};

struct registers struct_ILK_DPFC_STATUS[]={
	{NULL, 0},
};

struct registers struct_ILK_DPFC_FENCE_YOFF[]={
	{NULL, 0},
};

struct registers struct_ILK_DPFC_CHICKEN[]={
	{" ILK_FBC_RT_VALID ",ILK_FBC_RT_VALID },
	{NULL, 0},
};

struct registers struct_ILK_DISPLAY_CHICKEN1[]={
	{" ILK_FBCQ_DIS ",ILK_FBCQ_DIS },
	{" ILK_PABSTRETCH_DIS ",ILK_PABSTRETCH_DIS },
	{" SNB_CPU_FENCE_ENABLE ",SNB_CPU_FENCE_ENABLE },
	{" GMBUS_RATE_100KHZ ",GMBUS_RATE_100KHZ },
	{" GMBUS_RATE_50KHZ ",GMBUS_RATE_50KHZ },
	{" GMBUS_RATE_MASK ",GMBUS_RATE_MASK },
	{" GMBUS_PORT_DISABLED ",GMBUS_PORT_DISABLED },
	{" GMBUS_PORT_SSC ",GMBUS_PORT_SSC },
	{" GMBUS_PORT_VGADDC ",GMBUS_PORT_VGADDC },
	{" GMBUS_PORT_PANEL ",GMBUS_PORT_PANEL },
	{" GMBUS_PORT_DPC ",GMBUS_PORT_DPC },
	{" GMBUS_PORT_DPB ",GMBUS_PORT_DPB },
	{" GMBUS_PORT_DPD ",GMBUS_PORT_DPD },
	{" GMBUS_PORT_RESERVED ",GMBUS_PORT_RESERVED },
	{" GMBUS_NUM_PORTS ",GMBUS_NUM_PORTS },
	{" GMBUS_PORT_MASK ",GMBUS_PORT_MASK },
	{" GMBUS_SW_CLR_INT ",GMBUS_SW_CLR_INT },
	{" GMBUS_SW_RDY ",GMBUS_SW_RDY },
	{" GMBUS_CYCLE_NONE ",GMBUS_CYCLE_NONE },
	{" GMBUS_CYCLE_WAIT ",GMBUS_CYCLE_WAIT },
	{" GMBUS_CYCLE_INDEX ",GMBUS_CYCLE_INDEX },
	{" GMBUS_CYCLE_STOP ",GMBUS_CYCLE_STOP },
	{" GMBUS_BYTE_COUNT_SHIFT ",GMBUS_BYTE_COUNT_SHIFT },
	{" GMBUS_SLAVE_INDEX_SHIFT ",GMBUS_SLAVE_INDEX_SHIFT },
	{" GMBUS_SLAVE_ADDR_SHIFT ",GMBUS_SLAVE_ADDR_SHIFT },
	{" GMBUS_SLAVE_READ ",GMBUS_SLAVE_READ },
	{" GMBUS_SLAVE_WRITE ",GMBUS_SLAVE_WRITE },
	{" GMBUS_INUSE ",GMBUS_INUSE },
	{" GMBUS_HW_WAIT_PHASE ",GMBUS_HW_WAIT_PHASE },
	{" GMBUS_STALL_TIMEOUT ",GMBUS_STALL_TIMEOUT },
	{" GMBUS_INT ",GMBUS_INT },
	{" GMBUS_HW_RDY ",GMBUS_HW_RDY },
	{" GMBUS_SATOER ",GMBUS_SATOER },
	{" GMBUS_ACTIVE ",GMBUS_ACTIVE },
	{" GMBUS_SLAVE_TIMEOUT_EN ",GMBUS_SLAVE_TIMEOUT_EN },
	{" GMBUS_NAK_EN ",GMBUS_NAK_EN },
	{" GMBUS_IDLE_EN ",GMBUS_IDLE_EN },
	{" GMBUS_HW_WAIT_EN ",GMBUS_HW_WAIT_EN },
	{" GMBUS_HW_RDY_EN ",GMBUS_HW_RDY_EN },
	{" GMBUS_2BYTE_INDEX_EN ",GMBUS_2BYTE_INDEX_EN },
	{" VGA0_PD_P2_DIV_4 ",VGA0_PD_P2_DIV_4 },
	{" VGA0_PD_P1_DIV_2 ",VGA0_PD_P1_DIV_2 },
	{" VGA0_PD_P1_SHIFT ",VGA0_PD_P1_SHIFT },
	{" VGA1_PD_P2_DIV_4 ",VGA1_PD_P2_DIV_4 },
	{" VGA1_PD_P1_DIV_2 ",VGA1_PD_P1_DIV_2 },
	{" VGA1_PD_P1_SHIFT ",VGA1_PD_P1_SHIFT },
	{NULL, 0},
};

struct registers struct__DPLL_A[]={
	{NULL, 0},
};

struct registers struct__DPLL_B[]={
	{" DPLL_VCO_ENABLE ",DPLL_VCO_ENABLE },
	{" DPLL_DVO_HIGH_SPEED ",DPLL_DVO_HIGH_SPEED },
	{" DPLL_SYNCLOCK_ENABLE ",DPLL_SYNCLOCK_ENABLE },
	{" DPLL_VGA_MODE_DIS ",DPLL_VGA_MODE_DIS },
	{" DPLLB_MODE_DAC_SERIAL ",DPLLB_MODE_DAC_SERIAL },
	{" DPLLB_MODE_LVDS ",DPLLB_MODE_LVDS },
	{" DPLL_MODE_MASK ",DPLL_MODE_MASK },
	{" DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ",DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 },
	{" DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ",DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 },
	{" DPLLB_LVDS_P2_CLOCK_DIV_14 ",DPLLB_LVDS_P2_CLOCK_DIV_14 },
	{" DPLLB_LVDS_P2_CLOCK_DIV_7 ",DPLLB_LVDS_P2_CLOCK_DIV_7 },
	{" SR01 ",SR01 },
	{" SR01_SCREEN_OFF ",SR01_SCREEN_OFF },
	{NULL, 0},
};

struct registers struct_PPCR[]={
	{" PPCR_ON ",PPCR_ON },
	{NULL, 0},
};

struct registers struct_DVOB[]={
	{" DVOB_ON ",DVOB_ON },
	{NULL, 0},
};

struct registers struct_LVDS[]={
	{" LVDS_ON ",LVDS_ON },
	{" DPLL_FPA01_P1_POST_DIV_SHIFT ",DPLL_FPA01_P1_POST_DIV_SHIFT },
	{" DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW ",DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW },
	{" PLL_P2_DIVIDE_BY_4 ",PLL_P2_DIVIDE_BY_4 },
	{" PLL_P1_DIVIDE_BY_TWO ",PLL_P1_DIVIDE_BY_TWO },
	{" PLL_REF_INPUT_DREFCLK ",PLL_REF_INPUT_DREFCLK },
	{" PLL_REF_INPUT_TVCLKINA ",PLL_REF_INPUT_TVCLKINA },
	{" PLL_REF_INPUT_TVCLKINBC ",PLL_REF_INPUT_TVCLKINBC },
	{" PLLB_REF_INPUT_SPREADSPECTRUMIN ",PLLB_REF_INPUT_SPREADSPECTRUMIN },
	{" PLL_REF_INPUT_MASK ",PLL_REF_INPUT_MASK },
	{" PLL_LOAD_PULSE_PHASE_SHIFT ",PLL_LOAD_PULSE_PHASE_SHIFT },
	{" DISPLAY_RATE_SELECT_FPA1 ",DISPLAY_RATE_SELECT_FPA1 },
	{" SDVO_MULTIPLIER_SHIFT_HIRES ",SDVO_MULTIPLIER_SHIFT_HIRES },
	{" SDVO_MULTIPLIER_SHIFT_VGA ",SDVO_MULTIPLIER_SHIFT_VGA },
	{NULL, 0},
};

struct registers struct__DPLL_A_MD[]={
	{" DPLL_MD_UDI_DIVIDER_SHIFT ",DPLL_MD_UDI_DIVIDER_SHIFT },
	{" DPLL_MD_VGA_UDI_DIVIDER_SHIFT ",DPLL_MD_VGA_UDI_DIVIDER_SHIFT },
	{" DPLL_MD_UDI_MULTIPLIER_SHIFT ",DPLL_MD_UDI_MULTIPLIER_SHIFT },
	{" DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT ",DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT },
	{NULL, 0},
};

struct registers struct__DPLL_B_MD[]={
	{NULL, 0},
};

struct registers struct__FPA0[]={
	{NULL, 0},
};

struct registers struct__FPA1[]={
	{NULL, 0},
};

struct registers struct__FPB0[]={
	{NULL, 0},
};

struct registers struct__FPB1[]={
	{" FP_N_DIV_SHIFT ",FP_N_DIV_SHIFT },
	{" FP_M1_DIV_SHIFT ",FP_M1_DIV_SHIFT },
	{" FP_M2_DIV_SHIFT ",FP_M2_DIV_SHIFT },
	{" DPLLB_TEST_SDVO_DIV_1 ",DPLLB_TEST_SDVO_DIV_1 },
	{" DPLLB_TEST_SDVO_DIV_2 ",DPLLB_TEST_SDVO_DIV_2 },
	{" DPLLB_TEST_SDVO_DIV_4 ",DPLLB_TEST_SDVO_DIV_4 },
	{" DPLLB_TEST_SDVO_DIV_MASK ",DPLLB_TEST_SDVO_DIV_MASK },
	{" DPLLB_TEST_N_BYPASS ",DPLLB_TEST_N_BYPASS },
	{" DPLLB_TEST_M_BYPASS ",DPLLB_TEST_M_BYPASS },
	{" DPLLB_INPUT_BUFFER_ENABLE ",DPLLB_INPUT_BUFFER_ENABLE },
	{" DPLLA_TEST_N_BYPASS ",DPLLA_TEST_N_BYPASS },
	{" DPLLA_TEST_M_BYPASS ",DPLLA_TEST_M_BYPASS },
	{" DPLLA_INPUT_BUFFER_ENABLE ",DPLLA_INPUT_BUFFER_ENABLE },
	{" DSTATE_GFX_RESET_I830 ",DSTATE_GFX_RESET_I830 },
	{" DSTATE_PLL_D3_OFF ",DSTATE_PLL_D3_OFF },
	{" DSTATE_GFX_CLOCK_GATING ",DSTATE_GFX_CLOCK_GATING },
	{" DSTATE_DOT_CLOCK_GATING ",DSTATE_DOT_CLOCK_GATING },
	{" VF_UNIT_CLOCK_GATE_DISABLE ",VF_UNIT_CLOCK_GATE_DISABLE },
	{" GS_UNIT_CLOCK_GATE_DISABLE ",GS_UNIT_CLOCK_GATE_DISABLE },
	{" CL_UNIT_CLOCK_GATE_DISABLE ",CL_UNIT_CLOCK_GATE_DISABLE },
	{NULL, 0},
};

struct registers struct__PALETTE_A[]={
	{NULL, 0},
};

struct registers struct__PALETTE_B[]={
	{NULL, 0},
};

struct registers struct_MCHBAR_MIRROR_BASE[]={
	{NULL, 0},
};

struct registers struct_DCC[]={
	{" DCC_ADDRESSING_MODE_SINGLE_CHANNEL ",DCC_ADDRESSING_MODE_SINGLE_CHANNEL },
	{" DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC ",DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC },
	{" DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED ",DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED },
	{" DCC_ADDRESSING_MODE_MASK ",DCC_ADDRESSING_MODE_MASK },
	{" DCC_CHANNEL_XOR_DISABLE ",DCC_CHANNEL_XOR_DISABLE },
	{" DCC_CHANNEL_XOR_BIT_17 ",DCC_CHANNEL_XOR_BIT_17 },
	{NULL, 0},
};

struct registers struct_CSHRDDR3CTL[]={
	{" CSHRDDR3CTL_DDR3 ",CSHRDDR3CTL_DDR3 },
	{NULL, 0},
};

struct registers struct_C0DRB3[]={
	{NULL, 0},
};

struct registers struct_C1DRB3[]={
	{" MAD_DIMM_B_SIZE_SHIFT ",MAD_DIMM_B_SIZE_SHIFT },
	{" MAD_DIMM_A_SIZE_SHIFT ",MAD_DIMM_A_SIZE_SHIFT },
	{NULL, 0},
};

struct registers struct_CLKCFG[]={
	{" CLKCFG_FSB_400 ",CLKCFG_FSB_400 },
	{" CLKCFG_FSB_533 ",CLKCFG_FSB_533 },
	{" CLKCFG_FSB_667 ",CLKCFG_FSB_667 },
	{" CLKCFG_FSB_800 ",CLKCFG_FSB_800 },
	{" CLKCFG_FSB_1067 ",CLKCFG_FSB_1067 },
	{" CLKCFG_FSB_1333 ",CLKCFG_FSB_1333 },
	{" CLKCFG_FSB_1600 ",CLKCFG_FSB_1600 },
	{" CLKCFG_FSB_1600_ALT ",CLKCFG_FSB_1600_ALT },
	{" CLKCFG_FSB_MASK ",CLKCFG_FSB_MASK },
	{" CLKCFG_MEM_533 ",CLKCFG_MEM_533 },
	{" CLKCFG_MEM_667 ",CLKCFG_MEM_667 },
	{" CLKCFG_MEM_800 ",CLKCFG_MEM_800 },
	{" CLKCFG_MEM_MASK ",CLKCFG_MEM_MASK },
	{NULL, 0},
};

struct registers struct_TSC1[]={
	{" TSE ",TSE },
	{NULL, 0},
};

struct registers struct_TR1[]={
	{NULL, 0},
};

struct registers struct_TSFS[]={
	{" TSFS_SLOPE_SHIFT ",TSFS_SLOPE_SHIFT },
	{NULL, 0},
};

struct registers struct_CRSTANDVID[]={
	{NULL, 0},
};

struct registers struct_PXVFREQ_BASE[]={
	{" PXVFREQ_PX_SHIFT ",PXVFREQ_PX_SHIFT },
	{NULL, 0},
};

struct registers struct_VIDFREQ_BASE[]={
	{NULL, 0},
};

struct registers struct_VIDFREQ1[]={
	{NULL, 0},
};

struct registers struct_VIDFREQ2[]={
	{NULL, 0},
};

struct registers struct_VIDFREQ3[]={
	{NULL, 0},
};

struct registers struct_VIDFREQ4[]={
	{" VIDFREQ_P0_SHIFT ",VIDFREQ_P0_SHIFT },
	{" VIDFREQ_P0_CSCLK_SHIFT ",VIDFREQ_P0_CSCLK_SHIFT },
	{" VIDFREQ_P0_CRCLK_SHIFT ",VIDFREQ_P0_CRCLK_SHIFT },
	{" VIDFREQ_P1_SHIFT ",VIDFREQ_P1_SHIFT },
	{" VIDFREQ_P1_CSCLK_SHIFT ",VIDFREQ_P1_CSCLK_SHIFT },
	{NULL, 0},
};

struct registers struct_INTTOEXT_BASE_ILK[]={
	{NULL, 0},
};

struct registers struct_INTTOEXT_BASE[]={
	{" INTTOEXT_MAP3_SHIFT ",INTTOEXT_MAP3_SHIFT },
	{" INTTOEXT_MAP2_SHIFT ",INTTOEXT_MAP2_SHIFT },
	{" INTTOEXT_MAP1_SHIFT ",INTTOEXT_MAP1_SHIFT },
	{" INTTOEXT_MAP0_SHIFT ",INTTOEXT_MAP0_SHIFT },
	{NULL, 0},
};

struct registers struct_MEMSWCTL[]={
	{" MEMCTL_CMD_SHIFT ",MEMCTL_CMD_SHIFT },
	{" MEMCTL_CMD_RCLK_OFF ",MEMCTL_CMD_RCLK_OFF },
	{" MEMCTL_CMD_RCLK_ON ",MEMCTL_CMD_RCLK_ON },
	{" MEMCTL_CMD_CHFREQ ",MEMCTL_CMD_CHFREQ },
	{" MEMCTL_CMD_CHVID ",MEMCTL_CMD_CHVID },
	{" MEMCTL_CMD_VMMOFF ",MEMCTL_CMD_VMMOFF },
	{" MEMCTL_CMD_VMMON ",MEMCTL_CMD_VMMON },
	{" MEMCTL_FREQ_SHIFT ",MEMCTL_FREQ_SHIFT },
	{" MEMCTL_SFCAVM ",MEMCTL_SFCAVM },
	{NULL, 0},
};

struct registers struct_MEMIHYST[]={
	{NULL, 0},
};

struct registers struct_MEMINTREN[]={
	{" MEMINT_RSEXIT_EN ",MEMINT_RSEXIT_EN },
	{" MEMINT_CX_SUPR_EN ",MEMINT_CX_SUPR_EN },
	{" MEMINT_CONT_BUSY_EN ",MEMINT_CONT_BUSY_EN },
	{" MEMINT_AVG_BUSY_EN ",MEMINT_AVG_BUSY_EN },
	{" MEMINT_EVAL_CHG_EN ",MEMINT_EVAL_CHG_EN },
	{" MEMINT_MON_IDLE_EN ",MEMINT_MON_IDLE_EN },
	{" MEMINT_UP_EVAL_EN ",MEMINT_UP_EVAL_EN },
	{" MEMINT_DOWN_EVAL_EN ",MEMINT_DOWN_EVAL_EN },
	{" MEMINT_SW_CMD_EN ",MEMINT_SW_CMD_EN },
	{NULL, 0},
};

struct registers struct_MEMINTRSTR[]={
	{" MEM_RSEXIT_SHIFT ",MEM_RSEXIT_SHIFT },
	{" MEM_CONT_BUSY_SHIFT ",MEM_CONT_BUSY_SHIFT },
	{" MEM_AVG_BUSY_SHIFT ",MEM_AVG_BUSY_SHIFT },
	{" MEM_EVAL_BUSY_SHIFT ",MEM_EVAL_BUSY_SHIFT },
	{" MEM_MON_IDLE_SHIFT ",MEM_MON_IDLE_SHIFT },
	{" MEM_UP_EVAL_SHIFT ",MEM_UP_EVAL_SHIFT },
	{" MEM_DOWN_EVAL_SHIFT ",MEM_DOWN_EVAL_SHIFT },
	{" MEM_INT_STEER_GFX ",MEM_INT_STEER_GFX },
	{" MEM_INT_STEER_CMR ",MEM_INT_STEER_CMR },
	{" MEM_INT_STEER_SMI ",MEM_INT_STEER_SMI },
	{" MEM_INT_STEER_SCI ",MEM_INT_STEER_SCI },
	{NULL, 0},
};

struct registers struct_MEMINTRSTS[]={
	{" MEMINT_RSEXIT ",MEMINT_RSEXIT },
	{" MEMINT_CONT_BUSY ",MEMINT_CONT_BUSY },
	{" MEMINT_AVG_BUSY ",MEMINT_AVG_BUSY },
	{" MEMINT_EVAL_CHG ",MEMINT_EVAL_CHG },
	{" MEMINT_MON_IDLE ",MEMINT_MON_IDLE },
	{" MEMINT_UP_EVAL ",MEMINT_UP_EVAL },
	{" MEMINT_DOWN_EVAL ",MEMINT_DOWN_EVAL },
	{" MEMINT_SW_CMD ",MEMINT_SW_CMD },
	{NULL, 0},
};

struct registers struct_MEMMODECTL[]={
	{" MEMMODE_BOOST_EN ",MEMMODE_BOOST_EN },
	{" MEMMODE_BOOST_FREQ_SHIFT ",MEMMODE_BOOST_FREQ_SHIFT },
	{" MEMMODE_IDLE_MODE_SHIFT ",MEMMODE_IDLE_MODE_SHIFT },
	{" MEMMODE_IDLE_MODE_EVAL ",MEMMODE_IDLE_MODE_EVAL },
	{" MEMMODE_IDLE_MODE_CONT ",MEMMODE_IDLE_MODE_CONT },
	{" MEMMODE_HWIDLE_EN ",MEMMODE_HWIDLE_EN },
	{" MEMMODE_SWMODE_EN ",MEMMODE_SWMODE_EN },
	{" MEMMODE_RCLK_GATE ",MEMMODE_RCLK_GATE },
	{" MEMMODE_HW_UPDATE ",MEMMODE_HW_UPDATE },
	{" MEMMODE_FSTART_SHIFT ",MEMMODE_FSTART_SHIFT },
	{" MEMMODE_FMAX_SHIFT ",MEMMODE_FMAX_SHIFT },
	{NULL, 0},
};

struct registers struct_RCBMAXAVG[]={
	{NULL, 0},
};

struct registers struct_MEMSWCTL2[]={
	{" SWMEMCMD_RENDER_OFF ",SWMEMCMD_RENDER_OFF },
	{" SWMEMCMD_RENDER_ON ",SWMEMCMD_RENDER_ON },
	{" SWMEMCMD_SWFREQ ",SWMEMCMD_SWFREQ },
	{" SWMEMCMD_TARVID ",SWMEMCMD_TARVID },
	{" SWMEMCMD_VRM_OFF ",SWMEMCMD_VRM_OFF },
	{" SWMEMCMD_VRM_ON ",SWMEMCMD_VRM_ON },
	{" CMDSTS ",CMDSTS },
	{" SFCAVM ",SFCAVM },
	{" SWFREQ_SHIFT ",SWFREQ_SHIFT },
	{NULL, 0},
};

struct registers struct_MEMSTAT_CTG[]={
	{NULL, 0},
};

struct registers struct_RCBMINAVG[]={
	{NULL, 0},
};

struct registers struct_RCUPEI[]={
	{NULL, 0},
};

struct registers struct_RCDNEI[]={
	{NULL, 0},
};

struct registers struct_RSTDBYCTL[]={
	{" RS1EN ",RS1EN },
	{" RS2EN ",RS2EN },
	{" RS3EN ",RS3EN },
	{" D3RS3EN ",D3RS3EN },
	{" RSX_STATUS_MASK ",RSX_STATUS_MASK },
	{" RSX_STATUS_ON ",RSX_STATUS_ON },
	{" RSX_STATUS_RC1 ",RSX_STATUS_RC1 },
	{" RSX_STATUS_RC1E ",RSX_STATUS_RC1E },
	{" RSX_STATUS_RS1 ",RSX_STATUS_RS1 },
	{" RSX_STATUS_RS2 ",RSX_STATUS_RS2 },
	{" RSX_STATUS_RSVD2 ",RSX_STATUS_RSVD2 },
	{" RS1CONTSAV_MASK ",RS1CONTSAV_MASK },
	{" RS1CONTSAV_RSVD ",RS1CONTSAV_RSVD },
	{" NORMSLEXLAT_MASK ",NORMSLEXLAT_MASK },
	{" SLOW_RS123 ",SLOW_RS123 },
	{" SLOW_RS23 ",SLOW_RS23 },
	{" SLOW_RS3 ",SLOW_RS3 },
	{" NORMAL_RS123 ",NORMAL_RS123 },
	{" RCENTSYNC ",RCENTSYNC },
	{" STATELOCK ",STATELOCK },
	{" RS_CSTATE_MASK ",RS_CSTATE_MASK },
	{" RS_CSTATE_C367_RS1 ",RS_CSTATE_C367_RS1 },
	{" RS_CSTATE_C36_RS1_C7_RS2 ",RS_CSTATE_C36_RS1_C7_RS2 },
	{" RS_CSTATE_RSVD ",RS_CSTATE_RSVD },
	{" RS_CSTATE_C367_RS2 ",RS_CSTATE_C367_RS2 },
	{NULL, 0},
};

struct registers struct_VIDCTL[]={
	{NULL, 0},
};

struct registers struct_VIDSTS[]={
	{NULL, 0},
};

struct registers struct_VIDSTART[]={
	{NULL, 0},
};

struct registers struct_MEMSTAT_ILK[]={
	{" MEMSTAT_VID_SHIFT ",MEMSTAT_VID_SHIFT },
	{" MEMSTAT_PSTATE_SHIFT ",MEMSTAT_PSTATE_SHIFT },
	{" MEMSTAT_MON_ACTV ",MEMSTAT_MON_ACTV },
	{" MEMSTAT_SRC_CTL_CORE ",MEMSTAT_SRC_CTL_CORE },
	{" MEMSTAT_SRC_CTL_TRB ",MEMSTAT_SRC_CTL_TRB },
	{" MEMSTAT_SRC_CTL_THM ",MEMSTAT_SRC_CTL_THM },
	{" MEMSTAT_SRC_CTL_STDBY ",MEMSTAT_SRC_CTL_STDBY },
	{NULL, 0},
};

struct registers struct_RCPREVBSYTUPAVG[]={
	{NULL, 0},
};

struct registers struct_RCPREVBSYTDNAVG[]={
	{NULL, 0},
};

struct registers struct_PMMISC[]={
	{NULL, 0},
};

struct registers struct_SDEW[]={
	{NULL, 0},
};

struct registers struct_CSIEW0[]={
	{NULL, 0},
};

struct registers struct_CSIEW1[]={
	{NULL, 0},
};

struct registers struct_CSIEW2[]={
	{NULL, 0},
};

struct registers struct_PEW[]={
	{NULL, 0},
};

struct registers struct_DEW[]={
	{NULL, 0},
};

struct registers struct_MCHAFE[]={
	{NULL, 0},
};

struct registers struct_CSIEC[]={
	{NULL, 0},
};

struct registers struct_DMIEC[]={
	{NULL, 0},
};

struct registers struct_DDREC[]={
	{NULL, 0},
};

struct registers struct_PEG0EC[]={
	{NULL, 0},
};

struct registers struct_PEG1EC[]={
	{NULL, 0},
};

struct registers struct_GFXEC[]={
	{NULL, 0},
};

struct registers struct_RPPREVBSYTUPAVG[]={
	{NULL, 0},
};

struct registers struct_RPPREVBSYTDNAVG[]={
	{NULL, 0},
};

struct registers struct_ECR[]={
	{" ECR_GPFE ",ECR_GPFE },
	{" ECR_IMONE ",ECR_IMONE },
	{NULL, 0},
};

struct registers struct_OGW0[]={
	{NULL, 0},
};

struct registers struct_OGW1[]={
	{NULL, 0},
};

struct registers struct_EG0[]={
	{NULL, 0},
};

struct registers struct_EG1[]={
	{NULL, 0},
};

struct registers struct_EG2[]={
	{NULL, 0},
};

struct registers struct_EG3[]={
	{NULL, 0},
};

struct registers struct_EG4[]={
	{NULL, 0},
};

struct registers struct_EG5[]={
	{NULL, 0},
};

struct registers struct_EG6[]={
	{NULL, 0},
};

struct registers struct_EG7[]={
	{NULL, 0},
};

struct registers struct_PXW[]={
	{NULL, 0},
};

struct registers struct_PXWL[]={
	{NULL, 0},
};

struct registers struct_LCFUSE02[]={
	{NULL, 0},
};

struct registers struct_CSIPLL0[]={
	{" DDRMPLL1 ",DDRMPLL1 },
	{NULL, 0},
};

struct registers struct_PEG_BAND_GAP_DATA[]={
	{" CCID_EN ",CCID_EN },
	{NULL, 0},
};

struct registers struct_OVADD[]={
	{NULL, 0},
};

struct registers struct_DOVSTA[]={
	{NULL, 0},
};

struct registers struct_OGAMC5[]={
	{NULL, 0},
};

struct registers struct_OGAMC4[]={
	{NULL, 0},
};

struct registers struct_OGAMC3[]={
	{NULL, 0},
};

struct registers struct_OGAMC2[]={
	{NULL, 0},
};

struct registers struct_OGAMC1[]={
	{NULL, 0},
};

struct registers struct_OGAMC0[]={
	{NULL, 0},
};

struct registers struct__HTOTAL_A[]={
	{NULL, 0},
};

struct registers struct__HBLANK_A[]={
	{NULL, 0},
};

struct registers struct__HSYNC_A[]={
	{NULL, 0},
};

struct registers struct__VTOTAL_A[]={
	{NULL, 0},
};

struct registers struct__VBLANK_A[]={
	{NULL, 0},
};

struct registers struct__VSYNC_A[]={
	{NULL, 0},
};

struct registers struct__PIPEASRC[]={
	{NULL, 0},
};

struct registers struct__BCLRPAT_A[]={
	{NULL, 0},
};

struct registers struct__VSYNCSHIFT_A[]={
	{NULL, 0},
};

struct registers struct__HTOTAL_B[]={
	{NULL, 0},
};

struct registers struct__HBLANK_B[]={
	{NULL, 0},
};

struct registers struct__HSYNC_B[]={
	{NULL, 0},
};

struct registers struct__VTOTAL_B[]={
	{NULL, 0},
};

struct registers struct__VBLANK_B[]={
	{NULL, 0},
};

struct registers struct__VSYNC_B[]={
	{NULL, 0},
};

struct registers struct__PIPEBSRC[]={
	{NULL, 0},
};

struct registers struct__BCLRPAT_B[]={
	{NULL, 0},
};

struct registers struct__VSYNCSHIFT_B[]={
	{NULL, 0},
};

struct registers struct_ADPA[]={
	{" ADPA_DAC_ENABLE ",ADPA_DAC_ENABLE },
	{" ADPA_DAC_DISABLE ",ADPA_DAC_DISABLE },
	{" ADPA_PIPE_SELECT_MASK ",ADPA_PIPE_SELECT_MASK },
	{" ADPA_PIPE_A_SELECT ",ADPA_PIPE_A_SELECT },
	{" ADPA_PIPE_B_SELECT ",ADPA_PIPE_B_SELECT },
	{" ADPA_USE_VGA_HVPOLARITY ",ADPA_USE_VGA_HVPOLARITY },
	{" ADPA_SETS_HVPOLARITY ",ADPA_SETS_HVPOLARITY },
	{" ADPA_VSYNC_CNTL_DISABLE ",ADPA_VSYNC_CNTL_DISABLE },
	{" ADPA_VSYNC_CNTL_ENABLE ",ADPA_VSYNC_CNTL_ENABLE },
	{" ADPA_HSYNC_CNTL_DISABLE ",ADPA_HSYNC_CNTL_DISABLE },
	{" ADPA_HSYNC_CNTL_ENABLE ",ADPA_HSYNC_CNTL_ENABLE },
	{" ADPA_VSYNC_ACTIVE_HIGH ",ADPA_VSYNC_ACTIVE_HIGH },
	{" ADPA_VSYNC_ACTIVE_LOW ",ADPA_VSYNC_ACTIVE_LOW },
	{" ADPA_HSYNC_ACTIVE_HIGH ",ADPA_HSYNC_ACTIVE_HIGH },
	{" ADPA_HSYNC_ACTIVE_LOW ",ADPA_HSYNC_ACTIVE_LOW },
	{" ADPA_DPMS_MASK ",ADPA_DPMS_MASK },
	{" ADPA_DPMS_ON ",ADPA_DPMS_ON },
	{" ADPA_DPMS_SUSPEND ",ADPA_DPMS_SUSPEND },
	{" ADPA_DPMS_STANDBY ",ADPA_DPMS_STANDBY },
	{" ADPA_DPMS_OFF ",ADPA_DPMS_OFF },
	{NULL, 0},
};

struct registers struct_PORT_HOTPLUG_EN[]={
	{" HDMIB_HOTPLUG_INT_EN ",HDMIB_HOTPLUG_INT_EN },
	{" DPB_HOTPLUG_INT_EN ",DPB_HOTPLUG_INT_EN },
	{" HDMIC_HOTPLUG_INT_EN ",HDMIC_HOTPLUG_INT_EN },
	{" DPC_HOTPLUG_INT_EN ",DPC_HOTPLUG_INT_EN },
	{" HDMID_HOTPLUG_INT_EN ",HDMID_HOTPLUG_INT_EN },
	{" DPD_HOTPLUG_INT_EN ",DPD_HOTPLUG_INT_EN },
	{" SDVOB_HOTPLUG_INT_EN ",SDVOB_HOTPLUG_INT_EN },
	{" SDVOC_HOTPLUG_INT_EN ",SDVOC_HOTPLUG_INT_EN },
	{" TV_HOTPLUG_INT_EN ",TV_HOTPLUG_INT_EN },
	{" CRT_HOTPLUG_INT_EN ",CRT_HOTPLUG_INT_EN },
	{" CRT_HOTPLUG_FORCE_DETECT ",CRT_HOTPLUG_FORCE_DETECT },
	{" CRT_HOTPLUG_ACTIVATION_PERIOD_32 ",CRT_HOTPLUG_ACTIVATION_PERIOD_32 },
	{" CRT_HOTPLUG_ACTIVATION_PERIOD_64 ",CRT_HOTPLUG_ACTIVATION_PERIOD_64 },
	{" CRT_HOTPLUG_DAC_ON_TIME_2M ",CRT_HOTPLUG_DAC_ON_TIME_2M },
	{" CRT_HOTPLUG_DAC_ON_TIME_4M ",CRT_HOTPLUG_DAC_ON_TIME_4M },
	{" CRT_HOTPLUG_VOLTAGE_COMPARE_40 ",CRT_HOTPLUG_VOLTAGE_COMPARE_40 },
	{" CRT_HOTPLUG_VOLTAGE_COMPARE_50 ",CRT_HOTPLUG_VOLTAGE_COMPARE_50 },
	{" CRT_HOTPLUG_VOLTAGE_COMPARE_60 ",CRT_HOTPLUG_VOLTAGE_COMPARE_60 },
	{" CRT_HOTPLUG_VOLTAGE_COMPARE_70 ",CRT_HOTPLUG_VOLTAGE_COMPARE_70 },
	{" CRT_HOTPLUG_VOLTAGE_COMPARE_MASK ",CRT_HOTPLUG_VOLTAGE_COMPARE_MASK },
	{" CRT_HOTPLUG_DETECT_DELAY_1G ",CRT_HOTPLUG_DETECT_DELAY_1G },
	{" CRT_HOTPLUG_DETECT_DELAY_2G ",CRT_HOTPLUG_DETECT_DELAY_2G },
	{" CRT_HOTPLUG_DETECT_VOLTAGE_325MV ",CRT_HOTPLUG_DETECT_VOLTAGE_325MV },
	{" CRT_HOTPLUG_DETECT_VOLTAGE_475MV ",CRT_HOTPLUG_DETECT_VOLTAGE_475MV },
	{NULL, 0},
};

struct registers struct_PORT_HOTPLUG_STAT[]={
	{" HDMIB_HOTPLUG_INT_STATUS ",HDMIB_HOTPLUG_INT_STATUS },
	{" DPB_HOTPLUG_INT_STATUS ",DPB_HOTPLUG_INT_STATUS },
	{" HDMIC_HOTPLUG_INT_STATUS ",HDMIC_HOTPLUG_INT_STATUS },
	{" DPC_HOTPLUG_INT_STATUS ",DPC_HOTPLUG_INT_STATUS },
	{" HDMID_HOTPLUG_INT_STATUS ",HDMID_HOTPLUG_INT_STATUS },
	{" DPD_HOTPLUG_INT_STATUS ",DPD_HOTPLUG_INT_STATUS },
	{" CRT_HOTPLUG_INT_STATUS ",CRT_HOTPLUG_INT_STATUS },
	{" TV_HOTPLUG_INT_STATUS ",TV_HOTPLUG_INT_STATUS },
	{" CRT_HOTPLUG_MONITOR_MASK ",CRT_HOTPLUG_MONITOR_MASK },
	{" CRT_HOTPLUG_MONITOR_COLOR ",CRT_HOTPLUG_MONITOR_COLOR },
	{" CRT_HOTPLUG_MONITOR_MONO ",CRT_HOTPLUG_MONITOR_MONO },
	{" CRT_HOTPLUG_MONITOR_NONE ",CRT_HOTPLUG_MONITOR_NONE },

	{NULL, 0},
};

struct registers struct_SDVOB[]={
	{NULL, 0},
};

struct registers struct_SDVOC[]={
	{" SDVO_ENABLE ",SDVO_ENABLE },
	{" SDVO_PIPE_B_SELECT ",SDVO_PIPE_B_SELECT },
	{" SDVO_STALL_SELECT ",SDVO_STALL_SELECT },
	{" SDVO_INTERRUPT_ENABLE ",SDVO_INTERRUPT_ENABLE },
	{" SDVO_PORT_MULTIPLY_MASK ",SDVO_PORT_MULTIPLY_MASK },
	{" SDVO_PORT_MULTIPLY_SHIFT ",SDVO_PORT_MULTIPLY_SHIFT },
	{" SDVO_PHASE_SELECT_MASK ",SDVO_PHASE_SELECT_MASK },
	{" SDVO_PHASE_SELECT_DEFAULT ",SDVO_PHASE_SELECT_DEFAULT },
	{" SDVO_CLOCK_OUTPUT_INVERT ",SDVO_CLOCK_OUTPUT_INVERT },
	{" SDVOC_GANG_MODE ",SDVOC_GANG_MODE },
	{" SDVO_NULL_PACKETS_DURING_VSYNC ",SDVO_NULL_PACKETS_DURING_VSYNC },
	{" SDVO_COLOR_RANGE_16_235 ",SDVO_COLOR_RANGE_16_235 },
	{" SDVO_BORDER_ENABLE ",SDVO_BORDER_ENABLE },
	{" SDVO_AUDIO_ENABLE ",SDVO_AUDIO_ENABLE },
	{" SDVO_VSYNC_ACTIVE_HIGH ",SDVO_VSYNC_ACTIVE_HIGH },
	{" SDVO_HSYNC_ACTIVE_HIGH ",SDVO_HSYNC_ACTIVE_HIGH },
	{" SDVOB_PCIE_CONCURRENCY ",SDVOB_PCIE_CONCURRENCY },
	{" SDVO_DETECTED ",SDVO_DETECTED },
	{" SDVOB_PRESERVE_MASK ",SDVOB_PRESERVE_MASK },
	{" SDVOC_PRESERVE_MASK ",SDVOC_PRESERVE_MASK },
	{NULL, 0},
};

struct registers struct_DVOC[]={
	{" DVOC_ON ",DVOC_ON },
	{" DVO_ENABLE ",DVO_ENABLE },
	{" DVO_PIPE_B_SELECT ",DVO_PIPE_B_SELECT },
	{" DVO_PIPE_STALL_UNUSED ",DVO_PIPE_STALL_UNUSED },
	{" DVO_PIPE_STALL ",DVO_PIPE_STALL },
	{" DVO_PIPE_STALL_TV ",DVO_PIPE_STALL_TV },
	{" DVO_PIPE_STALL_MASK ",DVO_PIPE_STALL_MASK },
	{" DVO_USE_VGA_SYNC ",DVO_USE_VGA_SYNC },
	{" DVO_DATA_ORDER_I740 ",DVO_DATA_ORDER_I740 },
	{" DVO_DATA_ORDER_FP ",DVO_DATA_ORDER_FP },
	{" DVO_VSYNC_DISABLE ",DVO_VSYNC_DISABLE },
	{" DVO_HSYNC_DISABLE ",DVO_HSYNC_DISABLE },
	{" DVO_VSYNC_TRISTATE ",DVO_VSYNC_TRISTATE },
	{" DVO_HSYNC_TRISTATE ",DVO_HSYNC_TRISTATE },
	{" DVO_BORDER_ENABLE ",DVO_BORDER_ENABLE },
	{" DVO_DATA_ORDER_GBRG ",DVO_DATA_ORDER_GBRG },
	{" DVO_DATA_ORDER_RGGB ",DVO_DATA_ORDER_RGGB },
	{" DVO_DATA_ORDER_GBRG_ERRATA ",DVO_DATA_ORDER_GBRG_ERRATA },
	{" DVO_DATA_ORDER_RGGB_ERRATA ",DVO_DATA_ORDER_RGGB_ERRATA },
	{" DVO_VSYNC_ACTIVE_HIGH ",DVO_VSYNC_ACTIVE_HIGH },
	{" DVO_HSYNC_ACTIVE_HIGH ",DVO_HSYNC_ACTIVE_HIGH },
	{" DVO_BLANK_ACTIVE_HIGH ",DVO_BLANK_ACTIVE_HIGH },
	{NULL, 0},
};

struct registers struct_DVOA_SRCDIM[]={
	{NULL, 0},
};

struct registers struct_DVOB_SRCDIM[]={
	{NULL, 0},
};

struct registers struct_DVOC_SRCDIM[]={
	{" DVO_SRCDIM_HORIZONTAL_SHIFT ",DVO_SRCDIM_HORIZONTAL_SHIFT },
	{" DVO_SRCDIM_VERTICAL_SHIFT ",DVO_SRCDIM_VERTICAL_SHIFT },
	{NULL, 0},
};

struct registers struct_VIDEO_DIP_DATA[]={
	{NULL, 0},
};

struct registers struct_VIDEO_DIP_CTL[]={
	{" VIDEO_DIP_ENABLE ",VIDEO_DIP_ENABLE },
	{" VIDEO_DIP_PORT_B ",VIDEO_DIP_PORT_B },
	{" VIDEO_DIP_PORT_C ",VIDEO_DIP_PORT_C },
	{" VIDEO_DIP_ENABLE_AVI ",VIDEO_DIP_ENABLE_AVI },
	{" VIDEO_DIP_ENABLE_VENDOR ",VIDEO_DIP_ENABLE_VENDOR },
	{" VIDEO_DIP_ENABLE_SPD ",VIDEO_DIP_ENABLE_SPD },
	{" VIDEO_DIP_SELECT_AVI ",VIDEO_DIP_SELECT_AVI },
	{" VIDEO_DIP_SELECT_VENDOR ",VIDEO_DIP_SELECT_VENDOR },
	{" VIDEO_DIP_SELECT_SPD ",VIDEO_DIP_SELECT_SPD },
	{" VIDEO_DIP_SELECT_MASK ",VIDEO_DIP_SELECT_MASK },
	{" VIDEO_DIP_FREQ_ONCE ",VIDEO_DIP_FREQ_ONCE },
	{" VIDEO_DIP_FREQ_VSYNC ",VIDEO_DIP_FREQ_VSYNC },
	{" VIDEO_DIP_FREQ_2VSYNC ",VIDEO_DIP_FREQ_2VSYNC },
	{NULL, 0},
};

struct registers struct_PP_STATUS[]={
	{" PP_ON ",PP_ON },
	{" PP_READY ",PP_READY },
	{" PP_SEQUENCE_NONE ",PP_SEQUENCE_NONE },
	{" PP_SEQUENCE_POWER_UP ",PP_SEQUENCE_POWER_UP },
	{" PP_SEQUENCE_POWER_DOWN ",PP_SEQUENCE_POWER_DOWN },
	{" PP_SEQUENCE_MASK ",PP_SEQUENCE_MASK },
	{" PP_SEQUENCE_SHIFT ",PP_SEQUENCE_SHIFT },
	{" PP_CYCLE_DELAY_ACTIVE ",PP_CYCLE_DELAY_ACTIVE },
	{NULL, 0},
};

struct registers struct_PP_CONTROL[]={
	{" POWER_TARGET_ON ",POWER_TARGET_ON },
	{NULL, 0},
};

struct registers struct_PP_ON_DELAYS[]={
	{" T2 ", 0xffff0000, 0xffffffff, 1, 16},
	{" T5 ", 0xffff, 0xffffffff, 1, 0},
	{NULL, 0},
};

struct registers struct_PP_OFF_DELAYS[]={
	{" T3 ", 0xffff0000, 0xffffffff, 1, 16},
	{" Tx ", 0xffff, 0xffffffff, 1, 0},
	{NULL, 0},
};

struct registers struct_PP_DIVISOR[]={
	{NULL, 0},
};

struct registers struct_PFIT_CONTROL[]={
	{" PFIT_ENABLE ",PFIT_ENABLE },
	{" PFIT_PIPE_MASK ",PFIT_PIPE_MASK },
	{" PFIT_PIPE_SHIFT ",PFIT_PIPE_SHIFT },
	{" VERT_INTERP_DISABLE ",VERT_INTERP_DISABLE },
	{" VERT_INTERP_BILINEAR ",VERT_INTERP_BILINEAR },
	{" VERT_INTERP_MASK ",VERT_INTERP_MASK },
	{" VERT_AUTO_SCALE ",VERT_AUTO_SCALE },
	{" HORIZ_INTERP_DISABLE ",HORIZ_INTERP_DISABLE },
	{" HORIZ_INTERP_BILINEAR ",HORIZ_INTERP_BILINEAR },
	{" HORIZ_INTERP_MASK ",HORIZ_INTERP_MASK },
	{" HORIZ_AUTO_SCALE ",HORIZ_AUTO_SCALE },
	{" PANEL_8TO6_DITHER_ENABLE ",PANEL_8TO6_DITHER_ENABLE },
	{" PFIT_FILTER_FUZZY ",PFIT_FILTER_FUZZY },
	{" PFIT_SCALING_AUTO ",PFIT_SCALING_AUTO },
	{" PFIT_SCALING_PROGRAMMED ",PFIT_SCALING_PROGRAMMED },
	{" PFIT_SCALING_PILLAR ",PFIT_SCALING_PILLAR },
	{" PFIT_SCALING_LETTER ",PFIT_SCALING_LETTER },
	{NULL, 0},
};

struct registers struct_PFIT_PGM_RATIOS[]={
	{" PFIT_VERT_SCALE_SHIFT ",PFIT_VERT_SCALE_SHIFT },
	{" PFIT_HORIZ_SCALE_SHIFT ",PFIT_HORIZ_SCALE_SHIFT },
	{" PFIT_VERT_SCALE_SHIFT_965 ",PFIT_VERT_SCALE_SHIFT_965 },
	{" PFIT_HORIZ_SCALE_SHIFT_965 ",PFIT_HORIZ_SCALE_SHIFT_965 },
	{NULL, 0},
};

struct registers struct_PFIT_AUTO_RATIOS[]={
	{NULL, 0},
};

struct registers struct_BLC_PWM_CTL[]={
	{" BACKLIGHT_MODULATION_FREQ_SHIFT ",BACKLIGHT_MODULATION_FREQ_SHIFT },
	{NULL, 0},
};

struct registers struct_BLC_PWM_CTL2[]={
	{" BLM_COMBINATION_MODE ",BLM_COMBINATION_MODE },
	{" BLM_LEGACY_MODE ",BLM_LEGACY_MODE },
	{" BACKLIGHT_DUTY_CYCLE_SHIFT ",BACKLIGHT_DUTY_CYCLE_SHIFT },
	{NULL, 0},
};

struct registers struct_BLC_HIST_CTL[]={
	{NULL, 0},
};

struct registers struct_TV_CTL[]={
	{NULL, 0},
};

struct registers struct_TV_DAC[]={
	{NULL, 0},
};

struct registers struct_TV_CSC_Y[]={
	{NULL, 0},
};

struct registers struct_TV_CSC_Y2[]={
	{NULL, 0},
};

struct registers struct_TV_CSC_U[]={
	{NULL, 0},
};

struct registers struct_TV_CSC_U2[]={
	{NULL, 0},
};

struct registers struct_TV_CSC_V[]={
	{NULL, 0},
};

struct registers struct_TV_CSC_V2[]={
	{NULL, 0},
};

struct registers struct_TV_CLR_KNOBS[]={
	{NULL, 0},
};

struct registers struct_TV_CLR_LEVEL[]={
	{NULL, 0},
};

struct registers struct_TV_H_CTL_1[]={
	{NULL, 0},
};

struct registers struct_TV_H_CTL_2[]={
	{NULL, 0},
};

struct registers struct_TV_H_CTL_3[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_1[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_2[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_3[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_4[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_5[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_6[]={
	{NULL, 0},
};

struct registers struct_TV_V_CTL_7[]={
	{NULL, 0},
};

struct registers struct_TV_SC_CTL_1[]={
	{NULL, 0},
};

struct registers struct_TV_SC_CTL_2[]={
	{NULL, 0},
};

struct registers struct_TV_SC_CTL_3[]={
	{NULL, 0},
};

struct registers struct_TV_WIN_POS[]={
	{NULL, 0},
};

struct registers struct_TV_WIN_SIZE[]={
	{NULL, 0},
};

struct registers struct_TV_FILTER_CTL_1[]={
	{NULL, 0},
};

struct registers struct_TV_FILTER_CTL_2[]={
	{NULL, 0},
};

struct registers struct_TV_FILTER_CTL_3[]={
	{NULL, 0},
};

struct registers struct_TV_CC_CONTROL[]={
	{NULL, 0},
};

struct registers struct_TV_CC_DATA[]={
	{NULL, 0},
};

struct registers struct_TV_H_LUMA_0[]={
	{NULL, 0},
};

struct registers struct_TV_H_LUMA_59[]={
	{NULL, 0},
};

struct registers struct_TV_H_CHROMA_0[]={
	{NULL, 0},
};

struct registers struct_TV_H_CHROMA_59[]={
	{NULL, 0},
};

struct registers struct_TV_V_LUMA_0[]={
	{NULL, 0},
};

struct registers struct_TV_V_LUMA_42[]={
	{NULL, 0},
};

struct registers struct_TV_V_CHROMA_0[]={
	{NULL, 0},
};

struct registers struct_TV_V_CHROMA_42[]={
	{NULL, 0},
};

struct registers struct_DP_A[]={
	{NULL, 0},
};

struct registers struct_DP_B[]={
	{NULL, 0},
};

struct registers struct_DP_C[]={
	{NULL, 0},
};

struct registers struct_DP_D[]={
	{" DP_PORT_EN ",DP_PORT_EN },
	{" DP_PIPEB_SELECT ",DP_PIPEB_SELECT, DP_PIPE_MASK },
	{" DP_LINK_TRAIN_PAT_1 ",DP_LINK_TRAIN_PAT_1, DP_LINK_TRAIN_MASK },
	{" DP_LINK_TRAIN_PAT_2 ",DP_LINK_TRAIN_PAT_2, DP_LINK_TRAIN_MASK  },
	{" DP_LINK_TRAIN_PAT_IDLE ",DP_LINK_TRAIN_PAT_IDLE, DP_LINK_TRAIN_MASK  },
	{" DP_LINK_TRAIN_OFF ",DP_LINK_TRAIN_OFF, DP_LINK_TRAIN_MASK  },
	{" DP_LINK_TRAIN_PAT_1_CPT ",DP_LINK_TRAIN_PAT_1_CPT, DP_LINK_TRAIN_MASK_CPT },
	{" DP_LINK_TRAIN_PAT_2_CPT ",DP_LINK_TRAIN_PAT_2_CPT, DP_LINK_TRAIN_MASK_CPT  },
	{" DP_LINK_TRAIN_PAT_IDLE_CPT ",DP_LINK_TRAIN_PAT_IDLE_CPT, DP_LINK_TRAIN_MASK_CPT  },
	{" DP_LINK_TRAIN_OFF_CPT ",DP_LINK_TRAIN_OFF_CPT, DP_LINK_TRAIN_MASK_CPT  },
	{" DP_VOLTAGE_0_4 ",DP_VOLTAGE_0_4, DP_VOLTAGE_MASK },
	{" DP_VOLTAGE_0_6 ",DP_VOLTAGE_0_6, DP_VOLTAGE_MASK  },
	{" DP_VOLTAGE_0_8 ",DP_VOLTAGE_0_8, DP_VOLTAGE_MASK  },
	{" DP_VOLTAGE_1_2 ",DP_VOLTAGE_1_2, DP_VOLTAGE_MASK  },

	{" DP_PRE_EMPHASIS_0 ",DP_PRE_EMPHASIS_0, DP_PRE_EMPHASIS_MASK },
	{" DP_PRE_EMPHASIS_3_5 ",DP_PRE_EMPHASIS_3_5, DP_PRE_EMPHASIS_MASK  },
	{" DP_PRE_EMPHASIS_6 ",DP_PRE_EMPHASIS_6, DP_PRE_EMPHASIS_MASK  },
	{" DP_PRE_EMPHASIS_9_5 ",DP_PRE_EMPHASIS_9_5, DP_PRE_EMPHASIS_MASK  },

	{" DP_PORT_WIDTH_1 ",DP_PORT_WIDTH_1, DP_PORT_WIDTH_MASK },
	{" DP_PORT_WIDTH_2 ",DP_PORT_WIDTH_2, DP_PORT_WIDTH_MASK  },
	{" DP_PORT_WIDTH_4 ",DP_PORT_WIDTH_4, DP_PORT_WIDTH_MASK  },

	{" DP_ENHANCED_FRAMING ",DP_ENHANCED_FRAMING },
	{" DP_PLL_FREQ_270MHZ ",DP_PLL_FREQ_270MHZ, DP_PLL_FREQ_MASK},
	{" DP_PLL_FREQ_160MHZ ",DP_PLL_FREQ_160MHZ, DP_PLL_FREQ_MASK },

	{" DP_PORT_REVERSAL ",DP_PORT_REVERSAL },
	{" DP_PLL_ENABLE ",DP_PLL_ENABLE },
	{" DP_CLOCK_OUTPUT_ENABLE ",DP_CLOCK_OUTPUT_ENABLE },
	{" DP_SCRAMBLING_DISABLE ",DP_SCRAMBLING_DISABLE },
	{" DP_SCRAMBLING_DISABLE_IRONLAKE ",DP_SCRAMBLING_DISABLE_IRONLAKE },
	{" DP_COLOR_RANGE_16_235 ",DP_COLOR_RANGE_16_235 },
	{" DP_AUDIO_OUTPUT_ENABLE ",DP_AUDIO_OUTPUT_ENABLE },
	{" DP_SYNC_VS_HIGH ",DP_SYNC_VS_HIGH },
	{" DP_SYNC_HS_HIGH ",DP_SYNC_HS_HIGH },
	{" DP_DETECTED ",DP_DETECTED },
	{NULL, 0},
};

struct registers struct_DPA_AUX_CH_CTL[]={
	{" DP_AUX_CH_CTL_SEND_BUSY ",DP_AUX_CH_CTL_SEND_BUSY },
	{" DP_AUX_CH_CTL_DONE ",DP_AUX_CH_CTL_DONE },
	{" DP_AUX_CH_CTL_INTERRUPT ",DP_AUX_CH_CTL_INTERRUPT },
	{" DP_AUX_CH_CTL_TIME_OUT_ERROR ",DP_AUX_CH_CTL_TIME_OUT_ERROR },
	{" DP_AUX_CH_CTL_TIME_OUT_400us ",DP_AUX_CH_CTL_TIME_OUT_400us },
	{" DP_AUX_CH_CTL_TIME_OUT_600us ",DP_AUX_CH_CTL_TIME_OUT_600us },
	{" DP_AUX_CH_CTL_TIME_OUT_800us ",DP_AUX_CH_CTL_TIME_OUT_800us },
	{" DP_AUX_CH_CTL_TIME_OUT_1600us ",DP_AUX_CH_CTL_TIME_OUT_1600us },
	{" DP_AUX_CH_CTL_TIME_OUT_MASK ",DP_AUX_CH_CTL_TIME_OUT_MASK },
	{" DP_AUX_CH_CTL_RECEIVE_ERROR ",DP_AUX_CH_CTL_RECEIVE_ERROR },
	{" DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT ",DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT },
	{" DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT ",DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT },
	{" DP_AUX_CH_CTL_AUX_AKSV_SELECT ",DP_AUX_CH_CTL_AUX_AKSV_SELECT },
	{" DP_AUX_CH_CTL_MANCHESTER_TEST ",DP_AUX_CH_CTL_MANCHESTER_TEST },
	{" DP_AUX_CH_CTL_SYNC_TEST ",DP_AUX_CH_CTL_SYNC_TEST },
	{" DP_AUX_CH_CTL_DEGLITCH_TEST ",DP_AUX_CH_CTL_DEGLITCH_TEST },
	{" DP_AUX_CH_CTL_PRECHARGE_TEST ",DP_AUX_CH_CTL_PRECHARGE_TEST },
	{" DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT ",DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT },
	{NULL, 0},
};

struct registers struct_DPA_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_DPA_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_DPA_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_DPA_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_DPA_AUX_CH_DATA5[]={
	{NULL, 0},
};

struct registers struct_DPB_AUX_CH_CTL[]={
	{" DP_AUX_CH_CTL_SEND_BUSY ",DP_AUX_CH_CTL_SEND_BUSY },
	{" DP_AUX_CH_CTL_DONE ",DP_AUX_CH_CTL_DONE },
	{" DP_AUX_CH_CTL_INTERRUPT ",DP_AUX_CH_CTL_INTERRUPT },
	{" DP_AUX_CH_CTL_TIME_OUT_ERROR ",DP_AUX_CH_CTL_TIME_OUT_ERROR },
	{" DP_AUX_CH_CTL_TIME_OUT_400us ",DP_AUX_CH_CTL_TIME_OUT_400us },
	{" DP_AUX_CH_CTL_TIME_OUT_600us ",DP_AUX_CH_CTL_TIME_OUT_600us },
	{" DP_AUX_CH_CTL_TIME_OUT_800us ",DP_AUX_CH_CTL_TIME_OUT_800us },
	{" DP_AUX_CH_CTL_TIME_OUT_1600us ",DP_AUX_CH_CTL_TIME_OUT_1600us },
	{" DP_AUX_CH_CTL_TIME_OUT_MASK ",DP_AUX_CH_CTL_TIME_OUT_MASK },
	{" DP_AUX_CH_CTL_RECEIVE_ERROR ",DP_AUX_CH_CTL_RECEIVE_ERROR },
	{" DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT ",DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT },
	{" DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT ",DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT },
	{" DP_AUX_CH_CTL_AUX_AKSV_SELECT ",DP_AUX_CH_CTL_AUX_AKSV_SELECT },
	{" DP_AUX_CH_CTL_MANCHESTER_TEST ",DP_AUX_CH_CTL_MANCHESTER_TEST },
	{" DP_AUX_CH_CTL_SYNC_TEST ",DP_AUX_CH_CTL_SYNC_TEST },
	{" DP_AUX_CH_CTL_DEGLITCH_TEST ",DP_AUX_CH_CTL_DEGLITCH_TEST },
	{" DP_AUX_CH_CTL_PRECHARGE_TEST ",DP_AUX_CH_CTL_PRECHARGE_TEST },
	{" DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT ",DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT },
	{NULL, 0},
};

struct registers struct_DPB_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_DPB_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_DPB_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_DPB_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_DPB_AUX_CH_DATA5[]={
	{NULL, 0},
};

struct registers struct_DPC_AUX_CH_CTL[]={
	{" DP_AUX_CH_CTL_SEND_BUSY ",DP_AUX_CH_CTL_SEND_BUSY },
	{" DP_AUX_CH_CTL_DONE ",DP_AUX_CH_CTL_DONE },
	{" DP_AUX_CH_CTL_INTERRUPT ",DP_AUX_CH_CTL_INTERRUPT },
	{" DP_AUX_CH_CTL_TIME_OUT_ERROR ",DP_AUX_CH_CTL_TIME_OUT_ERROR },
	{" DP_AUX_CH_CTL_TIME_OUT_400us ",DP_AUX_CH_CTL_TIME_OUT_400us },
	{" DP_AUX_CH_CTL_TIME_OUT_600us ",DP_AUX_CH_CTL_TIME_OUT_600us },
	{" DP_AUX_CH_CTL_TIME_OUT_800us ",DP_AUX_CH_CTL_TIME_OUT_800us },
	{" DP_AUX_CH_CTL_TIME_OUT_1600us ",DP_AUX_CH_CTL_TIME_OUT_1600us },
	{" DP_AUX_CH_CTL_TIME_OUT_MASK ",DP_AUX_CH_CTL_TIME_OUT_MASK },
	{" DP_AUX_CH_CTL_RECEIVE_ERROR ",DP_AUX_CH_CTL_RECEIVE_ERROR },
	{" DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT ",DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT },
	{" DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT ",DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT },
	{" DP_AUX_CH_CTL_AUX_AKSV_SELECT ",DP_AUX_CH_CTL_AUX_AKSV_SELECT },
	{" DP_AUX_CH_CTL_MANCHESTER_TEST ",DP_AUX_CH_CTL_MANCHESTER_TEST },
	{" DP_AUX_CH_CTL_SYNC_TEST ",DP_AUX_CH_CTL_SYNC_TEST },
	{" DP_AUX_CH_CTL_DEGLITCH_TEST ",DP_AUX_CH_CTL_DEGLITCH_TEST },
	{" DP_AUX_CH_CTL_PRECHARGE_TEST ",DP_AUX_CH_CTL_PRECHARGE_TEST },
	{" DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT ",DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT },
	{NULL, 0},
};

struct registers struct_DPC_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_DPC_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_DPC_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_DPC_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_DPC_AUX_CH_DATA5[]={
	{NULL, 0},
};

struct registers struct_DPD_AUX_CH_CTL[]={
	{NULL, 0},
};

struct registers struct_DPD_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_DPD_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_DPD_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_DPD_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_DPD_AUX_CH_DATA5[]={
	{NULL, 0},
};

struct registers struct__PIPEA_GMCH_DATA_M[]={
	{NULL, 0},
};

struct registers struct__PIPEB_GMCH_DATA_M[]={
	{" PIPE_GMCH_DATA_M_TU_SIZE_SHIFT ",PIPE_GMCH_DATA_M_TU_SIZE_SHIFT },
	{NULL, 0},
};

struct registers struct__PIPEA_GMCH_DATA_N[]={
	{NULL, 0},
};

struct registers struct__PIPEB_GMCH_DATA_N[]={
	{NULL, 0},
};

struct registers struct__PIPEA_DP_LINK_M[]={
	{NULL, 0},
};

struct registers struct__PIPEB_DP_LINK_M[]={
	{NULL, 0},
};

struct registers struct__PIPEA_DP_LINK_N[]={
	{NULL, 0},
};

struct registers struct__PIPEB_DP_LINK_N[]={
	{NULL, 0},
};

struct registers struct__PIPEADSL[]={
	{NULL, 0},
};

struct registers struct__PIPEACONF[]={
	{" PIPECONF_ENABLE ",PIPECONF_ENABLE },
	{" PIPECONF_DISABLE ",PIPECONF_DISABLE },
	{" PIPECONF_DOUBLE_WIDE ",PIPECONF_DOUBLE_WIDE },
	{" I965_PIPECONF_ACTIVE ",I965_PIPECONF_ACTIVE },
	{" PIPECONF_FRAME_START_DELAY_MASK ",PIPECONF_FRAME_START_DELAY_MASK, 0xffffffff, 1, 27 },
	{" PIPECONF_SINGLE_WIDE ",PIPECONF_SINGLE_WIDE },
	{" PIPECONF_PIPE_UNLOCKED ",PIPECONF_PIPE_UNLOCKED },
	{" PIPECONF_PIPE_LOCKED ",PIPECONF_PIPE_LOCKED },
	{" PIPECONF_PALETTE ",PIPECONF_PALETTE },
	{" PIPECONF_GAMMA ",PIPECONF_GAMMA },
	{" PIPECONF_FORCE_BORDER ",PIPECONF_FORCE_BORDER },
	{" PIPECONF_INTERLACE_MASK ",PIPECONF_INTERLACE_MASK },
	{" PIPECONF_PROGRESSIVE ",PIPECONF_PROGRESSIVE },
	{" PIPECONF_INTERLACE_W_FIELD_INDICATION ",PIPECONF_INTERLACE_W_FIELD_INDICATION },
	{" PIPECONF_PFIT_PF_INTERLACED_ILK ",PIPECONF_PFIT_PF_INTERLACED_ILK },
	{" PIPECONF_INTERLACED_ILK ",PIPECONF_INTERLACED_ILK },
	{" PIPECONF_CXSR_DOWNCLOCK ",PIPECONF_CXSR_DOWNCLOCK },
	{" PIPECONF_BPP_8 ",PIPECONF_BPP_8, PIPECONF_BPP_MASK },
	{" PIPECONF_BPP_10 ",PIPECONF_BPP_10, PIPECONF_BPP_MASK },
	{" PIPECONF_BPP_6 ",PIPECONF_BPP_6, PIPECONF_BPP_MASK },
	{" PIPECONF_BPP_12 ",PIPECONF_BPP_12, PIPECONF_BPP_MASK },
	{" PIPECONF_DITHER_EN ",PIPECONF_DITHER_EN },
	{" PIPECONF_DITHER_TYPE_SP ",PIPECONF_DITHER_TYPE_SP, PIPECONF_DITHER_TYPE_MASK },
	{" PIPECONF_DITHER_TYPE_ST1 ",PIPECONF_DITHER_TYPE_ST1, PIPECONF_DITHER_TYPE_MASK },
	{" PIPECONF_DITHER_TYPE_ST2 ",PIPECONF_DITHER_TYPE_ST2, PIPECONF_DITHER_TYPE_MASK },
	{" PIPECONF_DITHER_TYPE_TEMP ",PIPECONF_DITHER_TYPE_TEMP, PIPECONF_DITHER_TYPE_MASK },
	{NULL, 0},
};

struct registers struct__PIPEASTAT[]={
	{" PIPE_FIFO_UNDERRUN_STATUS ",PIPE_FIFO_UNDERRUN_STATUS },
	{" PIPE_CRC_ERROR_ENABLE ",PIPE_CRC_ERROR_ENABLE },
	{" PIPE_CRC_DONE_ENABLE ",PIPE_CRC_DONE_ENABLE },
	{" PIPE_GMBUS_EVENT_ENABLE ",PIPE_GMBUS_EVENT_ENABLE },
	{" PIPE_HOTPLUG_INTERRUPT_ENABLE ",PIPE_HOTPLUG_INTERRUPT_ENABLE },
	{" PIPE_VSYNC_INTERRUPT_ENABLE ",PIPE_VSYNC_INTERRUPT_ENABLE },
	{" PIPE_DISPLAY_LINE_COMPARE_ENABLE ",PIPE_DISPLAY_LINE_COMPARE_ENABLE },
	{" PIPE_DPST_EVENT_ENABLE ",PIPE_DPST_EVENT_ENABLE },
	{" PIPE_LEGACY_BLC_EVENT_ENABLE ",PIPE_LEGACY_BLC_EVENT_ENABLE },
	{" PIPE_ODD_FIELD_INTERRUPT_ENABLE ",PIPE_ODD_FIELD_INTERRUPT_ENABLE },
	{" PIPE_EVEN_FIELD_INTERRUPT_ENABLE ",PIPE_EVEN_FIELD_INTERRUPT_ENABLE },
	{" PIPE_HOTPLUG_TV_INTERRUPT_ENABLE ",PIPE_HOTPLUG_TV_INTERRUPT_ENABLE },
	{" PIPE_START_VBLANK_INTERRUPT_ENABLE ",PIPE_START_VBLANK_INTERRUPT_ENABLE },
	{" PIPE_VBLANK_INTERRUPT_ENABLE ",PIPE_VBLANK_INTERRUPT_ENABLE },
	{" PIPE_OVERLAY_UPDATED_ENABLE ",PIPE_OVERLAY_UPDATED_ENABLE },
	{" PIPE_CRC_ERROR_INTERRUPT_STATUS ",PIPE_CRC_ERROR_INTERRUPT_STATUS },
	{" PIPE_CRC_DONE_INTERRUPT_STATUS ",PIPE_CRC_DONE_INTERRUPT_STATUS },
	{" PIPE_GMBUS_INTERRUPT_STATUS ",PIPE_GMBUS_INTERRUPT_STATUS },
	{" PIPE_HOTPLUG_INTERRUPT_STATUS ",PIPE_HOTPLUG_INTERRUPT_STATUS },
	{" PIPE_VSYNC_INTERRUPT_STATUS ",PIPE_VSYNC_INTERRUPT_STATUS },
	{" PIPE_DISPLAY_LINE_COMPARE_STATUS ",PIPE_DISPLAY_LINE_COMPARE_STATUS },
	{" PIPE_DPST_EVENT_STATUS ",PIPE_DPST_EVENT_STATUS },
	{" PIPE_LEGACY_BLC_EVENT_STATUS ",PIPE_LEGACY_BLC_EVENT_STATUS },
	{" PIPE_ODD_FIELD_INTERRUPT_STATUS ",PIPE_ODD_FIELD_INTERRUPT_STATUS },
	{" PIPE_EVEN_FIELD_INTERRUPT_STATUS ",PIPE_EVEN_FIELD_INTERRUPT_STATUS },
	{" PIPE_HOTPLUG_TV_INTERRUPT_STATUS ",PIPE_HOTPLUG_TV_INTERRUPT_STATUS },
	{" PIPE_START_VBLANK_INTERRUPT_STATUS ",PIPE_START_VBLANK_INTERRUPT_STATUS },
	{" PIPE_VBLANK_INTERRUPT_STATUS ",PIPE_VBLANK_INTERRUPT_STATUS },
	{" PIPE_OVERLAY_UPDATED_STATUS ",PIPE_OVERLAY_UPDATED_STATUS },
	{" PIPE_8BPC ",PIPE_8BPC },
	{" PIPE_10BPC ",PIPE_10BPC },
	{" PIPE_6BPC ",PIPE_6BPC },
	{" PIPE_12BPC ",PIPE_12BPC },
	{NULL, 0},
};

struct registers struct_DSPARB[]={
	{" DSPARB_CSTART_SHIFT ",DSPARB_CSTART_SHIFT },
	{" DSPARB_BSTART_SHIFT ",DSPARB_BSTART_SHIFT },
	{" DSPARB_AEND_SHIFT ",DSPARB_AEND_SHIFT },
	{NULL, 0},
};

struct registers struct_DSPFW1[]={
	{" DSPFW_SR_SHIFT ",DSPFW_SR_SHIFT },
	{" DSPFW_CURSORB_SHIFT ",DSPFW_CURSORB_SHIFT },
	{" DSPFW_PLANEB_SHIFT ",DSPFW_PLANEB_SHIFT },
	{NULL, 0},
};

struct registers struct_DSPFW2[]={
	{" DSPFW_CURSORA_SHIFT ",DSPFW_CURSORA_SHIFT },
	{NULL, 0},
};

struct registers struct_DSPFW3[]={
	{" DSPFW_HPLL_SR_EN ",DSPFW_HPLL_SR_EN },
	{" DSPFW_CURSOR_SR_SHIFT ",DSPFW_CURSOR_SR_SHIFT },
	{" PINEVIEW_SELF_REFRESH_EN ",PINEVIEW_SELF_REFRESH_EN },
	{" DSPFW_HPLL_CURSOR_SHIFT ",DSPFW_HPLL_CURSOR_SHIFT },
	{" G4X_FIFO_LINE_SIZE ",G4X_FIFO_LINE_SIZE },
	{" I915_FIFO_LINE_SIZE ",I915_FIFO_LINE_SIZE },
	{" I830_FIFO_LINE_SIZE ",I830_FIFO_LINE_SIZE },
	{" G4X_FIFO_SIZE ",G4X_FIFO_SIZE },
	{" I965_FIFO_SIZE ",I965_FIFO_SIZE },
	{" I945_FIFO_SIZE ",I945_FIFO_SIZE },
	{" I915_FIFO_SIZE ",I915_FIFO_SIZE },
	{" I830_FIFO_SIZE ",I830_FIFO_SIZE },
	{" PINEVIEW_FIFO_LINE_SIZE ",PINEVIEW_FIFO_LINE_SIZE },
	{" PINEVIEW_DFT_HPLLOFF_WM ",PINEVIEW_DFT_HPLLOFF_WM },
	{" PINEVIEW_GUARD_WM ",PINEVIEW_GUARD_WM },
	{" PINEVIEW_CURSOR_FIFO ",PINEVIEW_CURSOR_FIFO },
	{" PINEVIEW_CURSOR_DFT_WM ",PINEVIEW_CURSOR_DFT_WM },
	{" PINEVIEW_CURSOR_GUARD_WM ",PINEVIEW_CURSOR_GUARD_WM },
	{" I965_CURSOR_FIFO ",I965_CURSOR_FIFO },
	{" I965_CURSOR_MAX_WM ",I965_CURSOR_MAX_WM },
	{" I965_CURSOR_DFT_WM ",I965_CURSOR_DFT_WM },
	{NULL, 0},
};

struct registers struct_WM0_PIPEA_ILK[]={
	{" WM0_PIPE_PLANE_MASK",WM0_PIPE_PLANE_MASK, 0xffffffff},
	{" WM0_PIPE_SPRITE_MASK ",WM0_PIPE_SPRITE_MASK, 0xffffffff},
	{" WM0_PIPE_CURSOR_MASK", WM0_PIPE_CURSOR_MASK, 0xffffffff},
	{NULL, 0},
};

struct registers struct_WM0_PIPEB_ILK[]={
	{" WM0_PIPE_PLANE_MASK",WM0_PIPE_PLANE_MASK, 0xffffffff},
	{" WM0_PIPE_SPRITE_MASK ",WM0_PIPE_SPRITE_MASK, 0xffffffff},
	{" WM0_PIPE_CURSOR_MASK", WM0_PIPE_CURSOR_MASK, 0xffffffff},
	{NULL, 0},
};

struct registers struct_WM0_PIPEC_IVB[]={
	{" WM0_PIPE_PLANE_MASK",WM0_PIPE_PLANE_MASK, 0xffffffff},
	{" WM0_PIPE_SPRITE_MASK ",WM0_PIPE_SPRITE_MASK, 0xffffffff},
	{" WM0_PIPE_CURSOR_MASK", WM0_PIPE_CURSOR_MASK, 0xffffffff},
	{NULL, 0},
};

struct registers struct_WM1_LP_ILK[]={
	{" WMx_LP_SR_EN ",WM1_LP_SR_EN },
	{" WMx_LP_LATENCY ",WM1_LP_LATENCY_MASK,WM1_LP_LATENCY_MASK,1,WM1_LP_LATENCY_SHIFT},
	{" WMx_LP_FBC ",WM1_LP_FBC_MASK,WM1_LP_FBC_MASK, 1, WM1_LP_FBC_SHIFT},
	{" WMx_LP_SR ",WM1_LP_SR_MASK,WM1_LP_SR_MASK, 1, WM1_LP_SR_SHIFT},
	{" WMx_LP_CURSOR ",WM1_LP_CURSOR_MASK, WM1_LP_CURSOR_MASK, 1, 0 },
	{NULL, 0},
};

struct registers struct_WM2_LP_ILK[]={
	{" WM2_LP_EN ",WM2_LP_EN },
	{NULL, 0},
};

struct registers struct_WM3_LP_ILK[]={
	{" WM3_LP_EN ",WM3_LP_EN },
	{NULL, 0},
};

struct registers struct_WM1S_LP_ILK[]={
	{NULL, 0},
};

struct registers struct_WM2S_LP_IVB[]={
	{NULL, 0},
};

struct registers struct_WM3S_LP_IVB[]={
	{" WM1S_LP_EN ",WM1S_LP_EN },
	{NULL, 0},
};

struct registers struct_MLTR_ILK[]={
	{" MLTR_WM1_SHIFT ",MLTR_WM1_SHIFT },
	{" MLTR_WM2_SHIFT ",MLTR_WM2_SHIFT },
	{" ILK_DISPLAY_FIFO ",ILK_DISPLAY_FIFO },
	{" ILK_DISPLAY_MAXWM ",ILK_DISPLAY_MAXWM },
	{" ILK_DISPLAY_DFTWM ",ILK_DISPLAY_DFTWM },
	{" ILK_CURSOR_FIFO ",ILK_CURSOR_FIFO },
	{" ILK_CURSOR_MAXWM ",ILK_CURSOR_MAXWM },
	{" ILK_CURSOR_DFTWM ",ILK_CURSOR_DFTWM },
	{" ILK_DISPLAY_SR_FIFO ",ILK_DISPLAY_SR_FIFO },
	{" ILK_CURSOR_SR_FIFO ",ILK_CURSOR_SR_FIFO },
	{" ILK_CURSOR_DFT_SRWM ",ILK_CURSOR_DFT_SRWM },
	{" ILK_FIFO_LINE_SIZE ",ILK_FIFO_LINE_SIZE },
	{" SNB_DISPLAY_FIFO ",SNB_DISPLAY_FIFO },
	{" SNB_DISPLAY_DFTWM ",SNB_DISPLAY_DFTWM },
	{" SNB_CURSOR_FIFO ",SNB_CURSOR_FIFO },
	{" SNB_CURSOR_DFTWM ",SNB_CURSOR_DFTWM },
	{" SNB_DISPLAY_SR_FIFO ",SNB_DISPLAY_SR_FIFO },
	{" SNB_CURSOR_SR_FIFO ",SNB_CURSOR_SR_FIFO },
	{" SNB_CURSOR_DFT_SRWM ",SNB_CURSOR_DFT_SRWM },
	{" SNB_FIFO_LINE_SIZE ",SNB_FIFO_LINE_SIZE },
	{" SSKPD_WM0_SHIFT ",SSKPD_WM0_SHIFT },
	{" SSKPD_WM1_SHIFT ",SSKPD_WM1_SHIFT },
	{" SSKPD_WM2_SHIFT ",SSKPD_WM2_SHIFT },
	{" SSKPD_WM3_SHIFT ",SSKPD_WM3_SHIFT },
	{NULL, 0},
};
struct registers struct_DP_AUX_CH_CTL[] ={
	{"DP_AUX_CH_CTL_SEND_BUSY", DP_AUX_CH_CTL_SEND_BUSY},
	{"DP_AUX_CH_CTL_DONE", DP_AUX_CH_CTL_DONE},
	{"DP_AUX_CH_CTL_INTERRUPT", DP_AUX_CH_CTL_INTERRUPT},
	{"DP_AUX_CH_CTL_TIME_OUT_ERROR", DP_AUX_CH_CTL_TIME_OUT_ERROR},
	{"DP_AUX_CH_CTL_TIME_OUT_400us", DP_AUX_CH_CTL_TIME_OUT_400us},
	{"DP_AUX_CH_CTL_TIME_OUT_600us", DP_AUX_CH_CTL_TIME_OUT_600us},
	{"DP_AUX_CH_CTL_TIME_OUT_800us", DP_AUX_CH_CTL_TIME_OUT_800us},
	{"DP_AUX_CH_CTL_TIME_OUT_1600us", DP_AUX_CH_CTL_TIME_OUT_1600us},
	{"DP_AUX_CH_CTL_TIME_OUT_MASK", DP_AUX_CH_CTL_TIME_OUT_MASK},
	{"DP_AUX_CH_CTL_RECEIVE_ERROR", DP_AUX_CH_CTL_RECEIVE_ERROR},
	{"DP_AUX_CH_CTL_MESSAGE_SIZE_MASK", DP_AUX_CH_CTL_MESSAGE_SIZE_MASK},
	{"DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT", DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT},
	{"DP_AUX_CH_CTL_PRECHARGE_2US_MASK", DP_AUX_CH_CTL_PRECHARGE_2US_MASK},
	{"DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT", DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT},
	{"DP_AUX_CH_CTL_AUX_AKSV_SELECT", DP_AUX_CH_CTL_AUX_AKSV_SELECT},
	{"DP_AUX_CH_CTL_MANCHESTER_TEST", DP_AUX_CH_CTL_MANCHESTER_TEST},
	{"DP_AUX_CH_CTL_SYNC_TEST", DP_AUX_CH_CTL_SYNC_TEST},
	{"DP_AUX_CH_CTL_DEGLITCH_TEST", DP_AUX_CH_CTL_DEGLITCH_TEST},
	{"DP_AUX_CH_CTL_PRECHARGE_TEST", DP_AUX_CH_CTL_PRECHARGE_TEST},
	{"DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK", DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK},
	{"DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT", DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT},
};
struct registers struct__PIPEAFRAMEHIGH[]={
	{" PIPE_FRAME_HIGH_SHIFT ",PIPE_FRAME_HIGH_SHIFT },
	{NULL, 0},
};

struct registers struct__PIPEAFRAMEPIXEL[]={
	{" PIPE_FRAME_LOW_SHIFT ",PIPE_FRAME_LOW_SHIFT },
	{" PIPE_PIXEL_SHIFT ",PIPE_PIXEL_SHIFT },
	{NULL, 0},
};

struct registers struct__PIPEA_FRMCOUNT_GM45[]={
	{NULL, 0},
};

struct registers struct__PIPEA_FLIPCOUNT_GM45[]={
	{NULL, 0},
};

struct registers struct__CURACNTR[]={
	{" CURSOR_FORMAT_SHIFT ",CURSOR_FORMAT_SHIFT },
	{" CURSOR_MODE_64_ARGB_AX ",CURSOR_MODE_64_ARGB_AX },
	{" MCURSOR_PIPE_SELECT ",MCURSOR_PIPE_SELECT },
	{" MCURSOR_PIPE_B ",MCURSOR_PIPE_B },
	{" MCURSOR_GAMMA_ENABLE ",MCURSOR_GAMMA_ENABLE },
	{NULL, 0},
};

struct registers struct__CURABASE[]={
	{NULL, 0},
};

struct registers struct__CURAPOS[]={
	{NULL, 0},
};

struct registers struct_CURSOR_POS_MASK[]={
	{" CURSOR_X_SHIFT ",CURSOR_X_SHIFT },
	{" CURSOR_Y_SHIFT ",CURSOR_Y_SHIFT },
	{NULL, 0},
};

struct registers struct_CURSIZE[]={
	{NULL, 0},
};

struct registers struct__CURBCNTR[]={
	{NULL, 0},
};

struct registers struct__CURBBASE[]={
	{NULL, 0},
};

struct registers struct__CURBPOS[]={
	{NULL, 0},
};

struct registers struct__CURBCNTR_IVB[]={
	{NULL, 0},
};

struct registers struct__CURBBASE_IVB[]={
	{NULL, 0},
};

struct registers struct__CURBPOS_IVB[]={
	{NULL, 0},
};

struct registers struct__DSPACNTR[]={
	{" DISPLAY_PLANE_ENABLE ",DISPLAY_PLANE_ENABLE , 0x80000000},
	/* Sorry, but the code doesn't handle this well. I did not anticipate this setup.
	 * fixme someday
	{" DISPLAY_PLANE_DISABLE ",DISPLAY_PLANE_DISABLE, 0x80000000},
	 */
	{" DISPPLANE_GAMMA_ENABLE ",DISPPLANE_GAMMA_ENABLE, 0x40000000 },
	//{" DISPPLANE_GAMMA_DISABLE ",DISPPLANE_GAMMA_DISABLE, 0x40000000},
// fucking bug.	{" DISPPLANE_SEL_PIPE_MASK/*(0=A,1=B)*/ ", DISPPLANE_SEL_PIPE_MASK, DISPPLANE_SEL_PIPE_MASK, 1, DISPPLANE_SEL_PIPE_SHIFT},

	{" DISPPLANE_YUV422 ",DISPPLANE_YUV422, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_8BPP ",DISPPLANE_8BPP, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_BGRA555 ",DISPPLANE_BGRA555, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_BGRX555 ",DISPPLANE_BGRX555, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_BGRX565 ",DISPPLANE_BGRX565, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_BGRX888 ",DISPPLANE_BGRX888, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_BGRA888 ",DISPPLANE_BGRA888, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_RGBX101010 ",DISPPLANE_RGBX101010, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_RGBA101010 ",DISPPLANE_RGBA101010, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_BGRX101010 ",DISPPLANE_BGRX101010, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_RGBX161616 ",DISPPLANE_RGBX161616, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_RGBX888 ",DISPPLANE_RGBX888, DISPPLANE_PIXFORMAT_MASK, },
	{" DISPPLANE_RGBA888 ",DISPPLANE_RGBA888, DISPPLANE_PIXFORMAT_MASK, },

	{" DISPPLANE_SEL_PIPE_MASK ", DISPPLANE_SEL_PIPE_MASK, DISPPLANE_SEL_PIPE_MASK, 1, DISPPLANE_SEL_PIPE_SHIFT},
	{" DISPPLANE_STEREO_ENABLE ",DISPPLANE_STEREO_ENABLE },
	{" DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ ",DISPPLANE_TRICKLE_FEED_DISABLE },
	{" DISPPLANE_SRC_KEY_ENABLE ",DISPPLANE_SRC_KEY_ENABLE },
	{" DISPPLANE_LINE_DOUBLE ",DISPPLANE_LINE_DOUBLE },
	{" DISPPLANE_STEREO_POLARITY_FIRST ",DISPPLANE_STEREO_POLARITY_FIRST },
	{" DISPPLANE_STEREO_POLARITY_SECOND ",DISPPLANE_STEREO_POLARITY_SECOND },
	{" DISPPLANE_TILED ",DISPPLANE_TILED },
	{NULL, 0},
};

struct registers struct__DSPAADDR[]={
	{NULL, 0},
};

struct registers struct__DSPASTRIDE[]={
	{NULL, 0},
};

struct registers struct__DSPAPOS[]={
	{NULL, 0},
};

struct registers struct__DSPASIZE[]={
	{NULL, 0},
};

struct registers struct__DSPASURF[]={
	{NULL, 0},
};

struct registers struct__DSPATILEOFF[]={
	{NULL, 0},
};

struct registers struct_SWF00[]={
	{NULL, 0},
};

struct registers struct_SWF01[]={
	{NULL, 0},
};

struct registers struct_SWF02[]={
	{NULL, 0},
};

struct registers struct_SWF03[]={
	{NULL, 0},
};

struct registers struct_SWF04[]={
	{NULL, 0},
};

struct registers struct_SWF05[]={
	{NULL, 0},
};

struct registers struct_SWF06[]={
	{NULL, 0},
};

struct registers struct_SWF10[]={
	{NULL, 0},
};

struct registers struct_SWF11[]={
	{NULL, 0},
};

struct registers struct_SWF14[]={
	{NULL, 0},
};

struct registers struct_SWF30[]={
	{NULL, 0},
};

struct registers struct_SWF31[]={
	{NULL, 0},
};

struct registers struct_SWF32[]={
	{NULL, 0},
};

struct registers struct__PIPEBDSL[]={
	{NULL, 0},
};

struct registers struct__PIPEBCONF[]={
	{NULL, 0},
};

struct registers struct__PIPEBSTAT[]={
	{NULL, 0},
};

struct registers struct__PIPEBFRAMEHIGH[]={
	{NULL, 0},
};

struct registers struct__PIPEBFRAMEPIXEL[]={
	{NULL, 0},
};

struct registers struct__PIPEB_FRMCOUNT_GM45[]={
	{NULL, 0},
};

struct registers struct__PIPEB_FLIPCOUNT_GM45[]={
	{NULL, 0},
};

struct registers struct__DSPBCNTR[]={
	{" DISPPLANE_ALPHA_TRANS_ENABLE ",DISPPLANE_ALPHA_TRANS_ENABLE },
	{" DISPPLANE_ALPHA_TRANS_DISABLE ",DISPPLANE_ALPHA_TRANS_DISABLE },
	{" DISPPLANE_SPRITE_ABOVE_DISPLAY ",DISPPLANE_SPRITE_ABOVE_DISPLAY },
	{" DISPPLANE_SPRITE_ABOVE_OVERLAY ",DISPPLANE_SPRITE_ABOVE_OVERLAY },
	{NULL, 0},
};

struct registers struct__DSPBADDR[]={
	{NULL, 0},
};

struct registers struct__DSPBSTRIDE[]={
	{NULL, 0},
};

struct registers struct__DSPBPOS[]={
	{NULL, 0},
};

struct registers struct__DSPBSIZE[]={
	{NULL, 0},
};

struct registers struct__DSPBSURF[]={
	{NULL, 0},
};

struct registers struct__DSPBTILEOFF[]={
	{NULL, 0},
};

struct registers struct__DVSACNTR[]={
	{" DVS_ENABLE ",DVS_ENABLE },
	{" DVS_GAMMA_ENABLE ",DVS_GAMMA_ENABLE },
	{" DVS_PIXFORMAT_MASK ",DVS_PIXFORMAT_MASK },
	{" DVS_FORMAT_YUV422 ",DVS_FORMAT_YUV422 },
	{" DVS_FORMAT_RGBX101010 ",DVS_FORMAT_RGBX101010 },
	{" DVS_FORMAT_RGBX888 ",DVS_FORMAT_RGBX888 },
	{" DVS_FORMAT_RGBX161616 ",DVS_FORMAT_RGBX161616 },
	{" DVS_SOURCE_KEY ",DVS_SOURCE_KEY },
	{" DVS_RGB_ORDER_XBGR ",DVS_RGB_ORDER_XBGR },
	{" DVS_YUV_BYTE_ORDER_MASK ",DVS_YUV_BYTE_ORDER_MASK },
	{" DVS_YUV_ORDER_YUYV ",DVS_YUV_ORDER_YUYV },
	{" DVS_YUV_ORDER_UYVY ",DVS_YUV_ORDER_UYVY },
	{" DVS_YUV_ORDER_YVYU ",DVS_YUV_ORDER_YVYU },
	{" DVS_YUV_ORDER_VYUY ",DVS_YUV_ORDER_VYUY },
	{" DVS_DEST_KEY ",DVS_DEST_KEY },
	{" DVS_TRICKLE_FEED_DISABLE ",DVS_TRICKLE_FEED_DISABLE },
	{" DVS_TILED ",DVS_TILED },
	{NULL, 0},
};

struct registers struct__DVSALINOFF[]={
	{NULL, 0},
};

struct registers struct__DVSASTRIDE[]={
	{NULL, 0},
};

struct registers struct__DVSAPOS[]={
	{NULL, 0},
};

struct registers struct__DVSASIZE[]={
	{NULL, 0},
};

struct registers struct__DVSAKEYVAL[]={
	{NULL, 0},
};

struct registers struct__DVSAKEYMSK[]={
	{NULL, 0},
};

struct registers struct__DVSASURF[]={
	{NULL, 0},
};

struct registers struct__DVSAKEYMAXVAL[]={
	{NULL, 0},
};

struct registers struct__DVSATILEOFF[]={
	{NULL, 0},
};

struct registers struct__DVSASURFLIVE[]={
	{NULL, 0},
};

struct registers struct__DVSASCALE[]={
	{" DVS_SCALE_ENABLE ",DVS_SCALE_ENABLE },
	{" DVS_FILTER_MASK ",DVS_FILTER_MASK },
	{" DVS_FILTER_MEDIUM ",DVS_FILTER_MEDIUM },
	{" DVS_FILTER_ENHANCING ",DVS_FILTER_ENHANCING },
	{" DVS_FILTER_SOFTENING ",DVS_FILTER_SOFTENING },
	{" DVS_VERTICAL_OFFSET_ENABLE ",DVS_VERTICAL_OFFSET_ENABLE },
	{NULL, 0},
};

struct registers struct__DVSAGAMC[]={
	{NULL, 0},
};

struct registers struct__DVSBCNTR[]={
	{NULL, 0},
};

struct registers struct__DVSBLINOFF[]={
	{NULL, 0},
};

struct registers struct__DVSBSTRIDE[]={
	{NULL, 0},
};

struct registers struct__DVSBPOS[]={
	{NULL, 0},
};

struct registers struct__DVSBSIZE[]={
	{NULL, 0},
};

struct registers struct__DVSBKEYVAL[]={
	{NULL, 0},
};

struct registers struct__DVSBKEYMSK[]={
	{NULL, 0},
};

struct registers struct__DVSBSURF[]={
	{NULL, 0},
};

struct registers struct__DVSBKEYMAXVAL[]={
	{NULL, 0},
};

struct registers struct__DVSBTILEOFF[]={
	{NULL, 0},
};

struct registers struct__DVSBSURFLIVE[]={
	{NULL, 0},
};

struct registers struct__DVSBSCALE[]={
	{NULL, 0},
};

struct registers struct__DVSBGAMC[]={
	{NULL, 0},
};

struct registers struct__SPRA_CTL[]={
	{" SPRITE_ENABLE ",SPRITE_ENABLE },
	{" SPRITE_GAMMA_ENABLE ",SPRITE_GAMMA_ENABLE },
	{" SPRITE_PIXFORMAT_MASK ",SPRITE_PIXFORMAT_MASK },
	{" SPRITE_FORMAT_YUV422 ",SPRITE_FORMAT_YUV422 },
	{" SPRITE_FORMAT_RGBX101010 ",SPRITE_FORMAT_RGBX101010 },
	{" SPRITE_FORMAT_RGBX888 ",SPRITE_FORMAT_RGBX888 },
	{" SPRITE_FORMAT_RGBX161616 ",SPRITE_FORMAT_RGBX161616 },
	{" SPRITE_FORMAT_YUV444 ",SPRITE_FORMAT_YUV444 },
	{" SPRITE_CSC_ENABLE ",SPRITE_CSC_ENABLE },
	{" SPRITE_SOURCE_KEY ",SPRITE_SOURCE_KEY },
	{" SPRITE_YUV_TO_RGB_CSC_DISABLE ",SPRITE_YUV_TO_RGB_CSC_DISABLE },
	{" SPRITE_YUV_CSC_FORMAT_BT709 ",SPRITE_YUV_CSC_FORMAT_BT709 },
	{" SPRITE_YUV_BYTE_ORDER_MASK ",SPRITE_YUV_BYTE_ORDER_MASK },
	{" SPRITE_YUV_ORDER_YUYV ",SPRITE_YUV_ORDER_YUYV },
	{" SPRITE_YUV_ORDER_UYVY ",SPRITE_YUV_ORDER_UYVY },
	{" SPRITE_YUV_ORDER_YVYU ",SPRITE_YUV_ORDER_YVYU },
	{" SPRITE_YUV_ORDER_VYUY ",SPRITE_YUV_ORDER_VYUY },
	{" SPRITE_TRICKLE_FEED_DISABLE ",SPRITE_TRICKLE_FEED_DISABLE },
	{" SPRITE_INT_GAMMA_ENABLE ",SPRITE_INT_GAMMA_ENABLE },
	{" SPRITE_TILED ",SPRITE_TILED },
	{" SPRITE_DEST_KEY ",SPRITE_DEST_KEY },
	{NULL, 0},
};

struct registers struct__SPRA_LINOFF[]={
	{NULL, 0},
};

struct registers struct__SPRA_STRIDE[]={
	{NULL, 0},
};

struct registers struct__SPRA_POS[]={
	{NULL, 0},
};

struct registers struct__SPRA_SIZE[]={
	{NULL, 0},
};

struct registers struct__SPRA_KEYVAL[]={
	{NULL, 0},
};

struct registers struct__SPRA_KEYMSK[]={
	{NULL, 0},
};

struct registers struct__SPRA_SURF[]={
	{NULL, 0},
};

struct registers struct__SPRA_KEYMAX[]={
	{NULL, 0},
};

struct registers struct__SPRA_TILEOFF[]={
	{NULL, 0},
};

struct registers struct__SPRA_SCALE[]={
	{" SPRITE_SCALE_ENABLE ",SPRITE_SCALE_ENABLE },
	{" SPRITE_FILTER_MASK ",SPRITE_FILTER_MASK },
	{" SPRITE_FILTER_MEDIUM ",SPRITE_FILTER_MEDIUM },
	{" SPRITE_FILTER_ENHANCING ",SPRITE_FILTER_ENHANCING },
	{" SPRITE_FILTER_SOFTENING ",SPRITE_FILTER_SOFTENING },
	{" SPRITE_VERTICAL_OFFSET_ENABLE ",SPRITE_VERTICAL_OFFSET_ENABLE },
	{NULL, 0},
};

struct registers struct__SPRA_GAMC[]={
	{NULL, 0},
};

struct registers struct__SPRB_CTL[]={
	{NULL, 0},
};

struct registers struct__SPRB_LINOFF[]={
	{NULL, 0},
};

struct registers struct__SPRB_STRIDE[]={
	{NULL, 0},
};

struct registers struct__SPRB_POS[]={
	{NULL, 0},
};

struct registers struct__SPRB_SIZE[]={
	{NULL, 0},
};

struct registers struct__SPRB_KEYVAL[]={
	{NULL, 0},
};

struct registers struct__SPRB_KEYMSK[]={
	{NULL, 0},
};

struct registers struct__SPRB_SURF[]={
	{NULL, 0},
};

struct registers struct__SPRB_KEYMAX[]={
	{NULL, 0},
};

struct registers struct__SPRB_TILEOFF[]={
	{NULL, 0},
};

struct registers struct__SPRB_SCALE[]={
	{NULL, 0},
};

struct registers struct__SPRB_GAMC[]={
	{NULL, 0},
};

struct registers struct_VGACNTRL[]={
	{" VGA_DISP_DISABLE ", VGA_DISP_DISABLE},
	{" VGA_2X_MODE ", VGA_2X_MODE},
	{" VGA_PIPE_B_SELECT ", VGA_PIPE_B_SELECT},
	{NULL, 0},
};

struct registers struct_CPU_VGACNTRL[]={
	{NULL, 0},
};

struct registers struct_DIGITAL_PORT_HOTPLUG_CNTRL[]={
	{" DIGITAL_PORTA_HOTPLUG_ENABLE ",DIGITAL_PORTA_HOTPLUG_ENABLE },
	{" DIGITAL_PORTA_SHORT_PULSE_2MS ",DIGITAL_PORTA_SHORT_PULSE_2MS },
	{" DIGITAL_PORTA_SHORT_PULSE_4_5MS ",DIGITAL_PORTA_SHORT_PULSE_4_5MS },
	{" DIGITAL_PORTA_SHORT_PULSE_6MS ",DIGITAL_PORTA_SHORT_PULSE_6MS },
	{" DIGITAL_PORTA_SHORT_PULSE_100MS ",DIGITAL_PORTA_SHORT_PULSE_100MS },
	{" DIGITAL_PORTA_NO_DETECT ",DIGITAL_PORTA_NO_DETECT },
	{" DIGITAL_PORTA_LONG_PULSE_DETECT_MASK ",DIGITAL_PORTA_LONG_PULSE_DETECT_MASK },
	{" DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK ",DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK },
	{NULL, 0},
};

struct registers struct_RR_HW_CTL[]={
	{NULL, 0},
};

struct registers struct_FDI_PLL_BIOS_0[]={
	{NULL, 0},
};

struct registers struct_FDI_PLL_BIOS_1[]={
	{NULL, 0},
};

struct registers struct_FDI_PLL_BIOS_2[]={
	{NULL, 0},
};

struct registers struct_DISPLAY_PORT_PLL_BIOS_0[]={
	{NULL, 0},
};

struct registers struct_DISPLAY_PORT_PLL_BIOS_1[]={
	{NULL, 0},
};

struct registers struct_DISPLAY_PORT_PLL_BIOS_2[]={
	{NULL, 0},
};

struct registers struct_PCH_DSPCLK_GATE_D[]={
	{NULL, 0},
};

struct registers struct_PCH_3DCGDIS0[]={
	{NULL, 0},
};

struct registers struct_PCH_3DCGDIS1[]={
	{NULL, 0},
};

struct registers struct_FDI_PLL_FREQ_CTL[]={
	{" FDI_PLL_FREQ_CHANGE_REQUEST ",FDI_PLL_FREQ_CHANGE_REQUEST },
	{NULL, 0},
};

struct registers struct_FDI_PLL_FREQ_LOCK_LIMIT_MASK[]={
	{NULL, 0},
};

struct registers struct__PIPEA_DATA_M1[]={
	{" PIPE_DATA_M1_OFFSET ",PIPE_DATA_M1_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_DATA_N1[]={
	{" PIPE_DATA_N1_OFFSET ",PIPE_DATA_N1_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_DATA_M2[]={
	{" PIPE_DATA_M2_OFFSET ",PIPE_DATA_M2_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_DATA_N2[]={
	{" PIPE_DATA_N2_OFFSET ",PIPE_DATA_N2_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_LINK_M1[]={
	{" PIPE_LINK_M1_OFFSET ",PIPE_LINK_M1_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_LINK_N1[]={
	{" PIPE_LINK_N1_OFFSET ",PIPE_LINK_N1_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_LINK_M2[]={
	{" PIPE_LINK_M2_OFFSET ",PIPE_LINK_M2_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEA_LINK_N2[]={
	{" PIPE_LINK_N2_OFFSET ",PIPE_LINK_N2_OFFSET },
	{NULL, 0},
};

struct registers struct__PIPEB_DATA_M1[]={
	{NULL, 0},
};

struct registers struct__PIPEB_DATA_N1[]={
	{NULL, 0},
};

struct registers struct__PIPEB_DATA_M2[]={
	{NULL, 0},
};

struct registers struct__PIPEB_DATA_N2[]={
	{NULL, 0},
};

struct registers struct__PIPEB_LINK_M1[]={
	{NULL, 0},
};

struct registers struct__PIPEB_LINK_N1[]={
	{NULL, 0},
};

struct registers struct__PIPEB_LINK_M2[]={
	{NULL, 0},
};

struct registers struct__PIPEB_LINK_N2[]={
	{NULL, 0},
};

struct registers struct__PFA_CTL_1[]={
	{NULL, 0},
};

struct registers struct__PFB_CTL_1[]={
	{" PF_ENABLE ",PF_ENABLE },
	{" PF_FILTER_MASK ",PF_FILTER_MASK },
	{" PF_FILTER_PROGRAMMED ",PF_FILTER_PROGRAMMED },
	{" PF_FILTER_EDGE_ENHANCE ",PF_FILTER_EDGE_ENHANCE },
	{" PF_FILTER_EDGE_SOFTEN ",PF_FILTER_EDGE_SOFTEN },
	{NULL, 0},
};

struct registers struct__PFA_WIN_SZ[]={
	{NULL, 0},
};

struct registers struct__PFB_WIN_SZ[]={
	{NULL, 0},
};

struct registers struct__PFA_WIN_POS[]={
	{NULL, 0},
};

struct registers struct__PFB_WIN_POS[]={
	{NULL, 0},
};

struct registers struct__PFA_VSCALE[]={
	{NULL, 0},
};

struct registers struct__PFB_VSCALE[]={
	{NULL, 0},
};

struct registers struct__PFA_HSCALE[]={
	{NULL, 0},
};

struct registers struct__PFB_HSCALE[]={
	{NULL, 0},
};

struct registers struct__LGC_PALETTE_A[]={
	{NULL, 0},
};

struct registers struct__LGC_PALETTE_B[]={
	{" DE_MASTER_IRQ_CONTROL ",DE_MASTER_IRQ_CONTROL },
	{" DE_SPRITEB_FLIP_DONE ",DE_SPRITEB_FLIP_DONE },
	{" DE_SPRITEA_FLIP_DONE ",DE_SPRITEA_FLIP_DONE },
	{" DE_PLANEB_FLIP_DONE ",DE_PLANEB_FLIP_DONE },
	{" DE_PLANEA_FLIP_DONE ",DE_PLANEA_FLIP_DONE },
	{" DE_PCU_EVENT ",DE_PCU_EVENT },
	{" DE_GTT_FAULT ",DE_GTT_FAULT },
	{" DE_POISON ",DE_POISON },
	{" DE_PERFORM_COUNTER ",DE_PERFORM_COUNTER },
	{" DE_PCH_EVENT ",DE_PCH_EVENT },
	{" DE_AUX_CHANNEL_A ",DE_AUX_CHANNEL_A },
	{" DE_DP_A_HOTPLUG ",DE_DP_A_HOTPLUG },
	{" DE_GSE ",DE_GSE },
	{" DE_PIPEB_VBLANK ",DE_PIPEB_VBLANK },
	{" DE_PIPEB_EVEN_FIELD ",DE_PIPEB_EVEN_FIELD },
	{" DE_PIPEB_ODD_FIELD ",DE_PIPEB_ODD_FIELD },
	{" DE_PIPEB_LINE_COMPARE ",DE_PIPEB_LINE_COMPARE },
	{" DE_PIPEB_VSYNC ",DE_PIPEB_VSYNC },
	{" DE_PIPEB_FIFO_UNDERRUN ",DE_PIPEB_FIFO_UNDERRUN },
	{" DE_PIPEA_VBLANK ",DE_PIPEA_VBLANK },
	{" DE_PIPEA_EVEN_FIELD ",DE_PIPEA_EVEN_FIELD },
	{" DE_PIPEA_ODD_FIELD ",DE_PIPEA_ODD_FIELD },
	{" DE_PIPEA_LINE_COMPARE ",DE_PIPEA_LINE_COMPARE },
	{" DE_PIPEA_VSYNC ",DE_PIPEA_VSYNC },
	{" DE_PIPEA_FIFO_UNDERRUN ",DE_PIPEA_FIFO_UNDERRUN },
	{" DE_ERR_DEBUG_IVB ",DE_ERR_DEBUG_IVB },
	{" DE_GSE_IVB ",DE_GSE_IVB },
	{" DE_PCH_EVENT_IVB ",DE_PCH_EVENT_IVB },
	{" DE_DP_A_HOTPLUG_IVB ",DE_DP_A_HOTPLUG_IVB },
	{" DE_AUX_CHANNEL_A_IVB ",DE_AUX_CHANNEL_A_IVB },
	{" DE_SPRITEB_FLIP_DONE_IVB ",DE_SPRITEB_FLIP_DONE_IVB },
	{" DE_SPRITEA_FLIP_DONE_IVB ",DE_SPRITEA_FLIP_DONE_IVB },
	{" DE_PLANEB_FLIP_DONE_IVB ",DE_PLANEB_FLIP_DONE_IVB },
	{" DE_PLANEA_FLIP_DONE_IVB ",DE_PLANEA_FLIP_DONE_IVB },
	{" DE_PIPEB_VBLANK_IVB ",DE_PIPEB_VBLANK_IVB },
	{" DE_PIPEA_VBLANK_IVB ",DE_PIPEA_VBLANK_IVB },
	{NULL, 0},
};

struct registers struct_DEISR[]={
	{NULL, 0},
};

struct registers struct_DEIMR[]={
	{NULL, 0},
};

struct registers struct_DEIIR[]={
	{NULL, 0},
};

struct registers struct_DEIER[]={
	{" GT_PIPE_NOTIFY ",GT_PIPE_NOTIFY },
	{" GT_SYNC_STATUS ",GT_SYNC_STATUS },
	{" GT_USER_INTERRUPT ",GT_USER_INTERRUPT },
	{" GT_BSD_USER_INTERRUPT ",GT_BSD_USER_INTERRUPT },
	{" GT_GEN6_BSD_USER_INTERRUPT ",GT_GEN6_BSD_USER_INTERRUPT },
	{NULL, 0},
};

struct registers struct_GTISR[]={
	{NULL, 0},
};

struct registers struct_GTIMR[]={
	{NULL, 0},
};

struct registers struct_GTIIR[]={
	{NULL, 0},
};

struct registers struct_GTIER[]={
	{NULL, 0},
};

struct registers struct_ILK_DISPLAY_CHICKEN2[]={
	{" ILK_ELPIN_409_SELECT ",ILK_ELPIN_409_SELECT },
	{" ILK_DPARB_GATE ",ILK_DPARB_GATE },
	{" ILK_VSDPFD_FULL ",ILK_VSDPFD_FULL },
	{NULL, 0},
};

struct registers struct_ILK_DISPLAY_CHICKEN_FUSES[]={
	{" ILK_INTERNAL_GRAPHICS_DISABLE ",ILK_INTERNAL_GRAPHICS_DISABLE },
	{" ILK_INTERNAL_DISPLAY_DISABLE ",ILK_INTERNAL_DISPLAY_DISABLE },
	{" ILK_DISPLAY_DEBUG_DISABLE ",ILK_DISPLAY_DEBUG_DISABLE },
	{" ILK_HDCP_DISABLE ",ILK_HDCP_DISABLE },
	{" ILK_eDP_A_DISABLE ",ILK_eDP_A_DISABLE },
	{" ILK_DESKTOP ",ILK_DESKTOP },
	{NULL, 0},
};

struct registers struct_ILK_DSPCLK_GATE[]={
	{NULL, 0},
};

struct registers struct_IVB_CHICKEN3[]={
	{NULL, 0},
};

struct registers struct_DISP_ARB_CTL[]={
	{" DISP_TILE_SURFACE_SWIZZLING ",DISP_TILE_SURFACE_SWIZZLING },
	{" DISP_FBC_WM_DIS ",DISP_FBC_WM_DIS },
	{" GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB ",GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB },
	{" SDE_AUDIO_POWER_D ",SDE_AUDIO_POWER_D },
	{" SDE_AUDIO_POWER_C ",SDE_AUDIO_POWER_C },
	{" SDE_AUDIO_POWER_B ",SDE_AUDIO_POWER_B },
	{" SDE_AUDIO_POWER_SHIFT ",SDE_AUDIO_POWER_SHIFT },
	{" SDE_AUDIO_POWER_MASK ",SDE_AUDIO_POWER_MASK },
	{" SDE_GMBUS ",SDE_GMBUS },
	{" SDE_AUDIO_HDCP_TRANSB ",SDE_AUDIO_HDCP_TRANSB },
	{" SDE_AUDIO_HDCP_TRANSA ",SDE_AUDIO_HDCP_TRANSA },
	{" SDE_AUDIO_HDCP_MASK ",SDE_AUDIO_HDCP_MASK },
	{" SDE_AUDIO_TRANSB ",SDE_AUDIO_TRANSB },
	{" SDE_AUDIO_TRANSA ",SDE_AUDIO_TRANSA },
	{" SDE_AUDIO_TRANS_MASK ",SDE_AUDIO_TRANS_MASK },
	{" SDE_POISON ",SDE_POISON },
	{" SDE_FDI_RXB ",SDE_FDI_RXB },
	{" SDE_FDI_RXA ",SDE_FDI_RXA },
	{" SDE_FDI_MASK ",SDE_FDI_MASK },
	{" SDE_AUXD ",SDE_AUXD },
	{" SDE_AUXC ",SDE_AUXC },
	{" SDE_AUXB ",SDE_AUXB },
	{" SDE_AUX_MASK ",SDE_AUX_MASK },
	{" SDE_CRT_HOTPLUG ",SDE_CRT_HOTPLUG },
	{" SDE_PORTD_HOTPLUG ",SDE_PORTD_HOTPLUG },
	{" SDE_PORTC_HOTPLUG ",SDE_PORTC_HOTPLUG },
	{" SDE_PORTB_HOTPLUG ",SDE_PORTB_HOTPLUG },
	{" SDE_SDVOB_HOTPLUG ",SDE_SDVOB_HOTPLUG },
	{" SDE_TRANSB_CRC_DONE ",SDE_TRANSB_CRC_DONE },
	{" SDE_TRANSB_CRC_ERR ",SDE_TRANSB_CRC_ERR },
	{" SDE_TRANSB_FIFO_UNDER ",SDE_TRANSB_FIFO_UNDER },
	{" SDE_TRANSA_CRC_DONE ",SDE_TRANSA_CRC_DONE },
	{" SDE_TRANSA_CRC_ERR ",SDE_TRANSA_CRC_ERR },
	{" SDE_TRANSA_FIFO_UNDER ",SDE_TRANSA_FIFO_UNDER },
	{" SDE_CRT_HOTPLUG_CPT ",SDE_CRT_HOTPLUG_CPT },
	{" SDE_PORTD_HOTPLUG_CPT ",SDE_PORTD_HOTPLUG_CPT },
	{" SDE_PORTC_HOTPLUG_CPT ",SDE_PORTC_HOTPLUG_CPT },
	{" SDE_PORTB_HOTPLUG_CPT ",SDE_PORTB_HOTPLUG_CPT },
	{" SDE_HOTPLUG_MASK_CPT ",SDE_HOTPLUG_MASK_CPT },
	{NULL, 0},
};

struct registers struct_SDEISR[]={
	{NULL, 0},
};

struct registers struct_SDEIMR[]={
	{NULL, 0},
};

struct registers struct_SDEIIR[]={
	{NULL, 0},
};

struct registers struct_SDEIER[]={
	{NULL, 0},
};

struct registers struct_PCH_PORT_HOTPLUG[]={
	{" PORTD_HOTPLUG_ENABLE ",PORTD_HOTPLUG_ENABLE },
	{" PORTD_PULSE_DURATION_2ms ",PORTD_PULSE_DURATION_2ms },
	{" PORTD_PULSE_DURATION_4_5ms ",PORTD_PULSE_DURATION_4_5ms },
	{" PORTD_PULSE_DURATION_6ms ",PORTD_PULSE_DURATION_6ms },
	{" PORTD_PULSE_DURATION_100ms ",PORTD_PULSE_DURATION_100ms },
	{" PORTD_PULSE_DURATION_MASK ",PORTD_PULSE_DURATION_MASK },
	{" PORTD_HOTPLUG_NO_DETECT ",PORTD_HOTPLUG_NO_DETECT },
	{" PORTD_HOTPLUG_SHORT_DETECT ",PORTD_HOTPLUG_SHORT_DETECT },
	{" PORTD_HOTPLUG_LONG_DETECT ",PORTD_HOTPLUG_LONG_DETECT },
	{" PORTC_HOTPLUG_ENABLE ",PORTC_HOTPLUG_ENABLE },
	{" PORTC_PULSE_DURATION_2ms ",PORTC_PULSE_DURATION_2ms },
	{" PORTC_PULSE_DURATION_4_5ms ",PORTC_PULSE_DURATION_4_5ms },
	{" PORTC_PULSE_DURATION_6ms ",PORTC_PULSE_DURATION_6ms },
	{" PORTC_PULSE_DURATION_100ms ",PORTC_PULSE_DURATION_100ms },
	{" PORTC_PULSE_DURATION_MASK ",PORTC_PULSE_DURATION_MASK },
	{" PORTC_HOTPLUG_NO_DETECT ",PORTC_HOTPLUG_NO_DETECT },
	{" PORTC_HOTPLUG_SHORT_DETECT ",PORTC_HOTPLUG_SHORT_DETECT },
	{" PORTC_HOTPLUG_LONG_DETECT ",PORTC_HOTPLUG_LONG_DETECT },
	{" PORTB_HOTPLUG_ENABLE ",PORTB_HOTPLUG_ENABLE },
	{" PORTB_PULSE_DURATION_2ms ",PORTB_PULSE_DURATION_2ms },
	{" PORTB_PULSE_DURATION_4_5ms ",PORTB_PULSE_DURATION_4_5ms },
	{" PORTB_PULSE_DURATION_6ms ",PORTB_PULSE_DURATION_6ms },
	{" PORTB_PULSE_DURATION_100ms ",PORTB_PULSE_DURATION_100ms },
	{" PORTB_PULSE_DURATION_MASK ",PORTB_PULSE_DURATION_MASK },
	{" PORTB_HOTPLUG_NO_DETECT ",PORTB_HOTPLUG_NO_DETECT },
	{" PORTB_HOTPLUG_SHORT_DETECT ",PORTB_HOTPLUG_SHORT_DETECT },
	{" PORTB_HOTPLUG_LONG_DETECT ",PORTB_HOTPLUG_LONG_DETECT },
	{NULL, 0},
};

struct registers struct_PCH_GPIOA[]={
	{NULL, 0},
};

struct registers struct_PCH_GPIOB[]={
	{NULL, 0},
};

struct registers struct_PCH_GPIOC[]={
	{NULL, 0},
};

struct registers struct_PCH_GPIOD[]={
	{NULL, 0},
};

struct registers struct_PCH_GPIOE[]={
	{NULL, 0},
};

struct registers struct_PCH_GPIOF[]={
	{NULL, 0},
};

struct registers struct_PCH_GMBUS0[]={
	{NULL, 0},
};

struct registers struct_PCH_GMBUS1[]={
	{NULL, 0},
};

struct registers struct_PCH_GMBUS2[]={
	{NULL, 0},
};

struct registers struct_PCH_GMBUS3[]={
	{NULL, 0},
};

struct registers struct_PCH_GMBUS4[]={
	{NULL, 0},
};

struct registers struct_PCH_GMBUS5[]={
	{NULL, 0},
};

struct registers struct__PCH_DPLL_A[]={
	{NULL, 0},
};

struct registers struct__PCH_DPLL_B[]={
	{NULL, 0},
};

struct registers struct__PCH_FPA0[]={
	{NULL, 0},
};

struct registers struct__PCH_FPA1[]={
	{NULL, 0},
};

struct registers struct__PCH_FPB0[]={
	{NULL, 0},
};

struct registers struct__PCH_FPB1[]={
	{NULL, 0},
};

struct registers struct_PCH_DPLL_TEST[]={
	{NULL, 0},
};

struct registers struct_PCH_DREF_CONTROL[]={
	{" DREF_CPU_SOURCE_OUTPUT_DISABLE ",DREF_CPU_SOURCE_OUTPUT_DISABLE },
	{" DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD ",DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD },
	{" DREF_CPU_SOURCE_OUTPUT_NONSPREAD ",DREF_CPU_SOURCE_OUTPUT_NONSPREAD },
	{" DREF_CPU_SOURCE_OUTPUT_MASK ",DREF_CPU_SOURCE_OUTPUT_MASK },
	{" DREF_SSC_SOURCE_DISABLE ",DREF_SSC_SOURCE_DISABLE },
	{" DREF_SSC_SOURCE_ENABLE ",DREF_SSC_SOURCE_ENABLE },
	{" DREF_SSC_SOURCE_MASK ",DREF_SSC_SOURCE_MASK },
	{" DREF_NONSPREAD_SOURCE_DISABLE ",DREF_NONSPREAD_SOURCE_DISABLE },
	{" DREF_NONSPREAD_CK505_ENABLE ",DREF_NONSPREAD_CK505_ENABLE },
	{" DREF_NONSPREAD_SOURCE_ENABLE ",DREF_NONSPREAD_SOURCE_ENABLE },
	{" DREF_NONSPREAD_SOURCE_MASK ",DREF_NONSPREAD_SOURCE_MASK },
	{" DREF_SUPERSPREAD_SOURCE_DISABLE ",DREF_SUPERSPREAD_SOURCE_DISABLE },
	{" DREF_SUPERSPREAD_SOURCE_ENABLE ",DREF_SUPERSPREAD_SOURCE_ENABLE },
	{" DREF_SUPERSPREAD_SOURCE_MASK ",DREF_SUPERSPREAD_SOURCE_MASK },
	{" DREF_SSC4_DOWNSPREAD ",DREF_SSC4_DOWNSPREAD },
	{" DREF_SSC4_CENTERSPREAD ",DREF_SSC4_CENTERSPREAD },
	{" DREF_SSC1_DISABLE ",DREF_SSC1_DISABLE },
	{" DREF_SSC1_ENABLE ",DREF_SSC1_ENABLE },
	{" DREF_SSC4_DISABLE ",DREF_SSC4_DISABLE },
	{" DREF_SSC4_ENABLE ",DREF_SSC4_ENABLE },
	{NULL, 0},
};

struct registers struct_PCH_RAWCLK_FREQ[]={
	{" FDL_TP1_TIMER_SHIFT ",FDL_TP1_TIMER_SHIFT },
	{" FDL_TP1_TIMER_MASK ",FDL_TP1_TIMER_MASK },
	{" FDL_TP2_TIMER_SHIFT ",FDL_TP2_TIMER_SHIFT },
	{" FDL_TP2_TIMER_MASK ",FDL_TP2_TIMER_MASK },
	{NULL, 0},
};

struct registers struct_PCH_DPLL_TMR_CFG[]={
	{NULL, 0},
};

struct registers struct_PCH_SSC4_PARMS[]={
	{NULL, 0},
};

struct registers struct_PCH_SSC4_AUX_PARMS[]={
	{NULL, 0},
};

struct registers struct_PCH_DPLL_SEL[]={
	{" TRANSA_DPLL_ENABLE ",TRANSA_DPLL_ENABLE },
	{" TRANSA_DPLLB_SEL ",TRANSA_DPLLB_SEL },
	{" TRANSA_DPLLA_SEL ",TRANSA_DPLLA_SEL },
	{" TRANSB_DPLL_ENABLE ",TRANSB_DPLL_ENABLE },
	{" TRANSB_DPLLB_SEL ",TRANSB_DPLLB_SEL },
	{" TRANSB_DPLLA_SEL ",TRANSB_DPLLA_SEL },
	{" TRANSC_DPLL_ENABLE ",TRANSC_DPLL_ENABLE },
	{" TRANSC_DPLLB_SEL ",TRANSC_DPLLB_SEL },
	{" TRANSC_DPLLA_SEL ",TRANSC_DPLLA_SEL },
	{NULL, 0},
};

struct registers struct__TRANS_HTOTAL_A[]={
	{" TRANS_HTOTAL_SHIFT ",TRANS_HTOTAL_SHIFT },
	{" TRANS_HACTIVE_SHIFT ",TRANS_HACTIVE_SHIFT },
	{NULL, 0},
};

struct registers struct__TRANS_HBLANK_A[]={
	{" TRANS_HBLANK_END_SHIFT ",TRANS_HBLANK_END_SHIFT },
	{" TRANS_HBLANK_START_SHIFT ",TRANS_HBLANK_START_SHIFT },
	{NULL, 0},
};

struct registers struct__TRANS_HSYNC_A[]={
	{" TRANS_HSYNC_END_SHIFT ",TRANS_HSYNC_END_SHIFT },
	{" TRANS_HSYNC_START_SHIFT ",TRANS_HSYNC_START_SHIFT },
	{NULL, 0},
};

struct registers struct__TRANS_VTOTAL_A[]={
	{" TRANS_VTOTAL_SHIFT ",TRANS_VTOTAL_SHIFT },
	{" TRANS_VACTIVE_SHIFT ",TRANS_VACTIVE_SHIFT },
	{NULL, 0},
};

struct registers struct__TRANS_VBLANK_A[]={
	{" TRANS_VBLANK_END_SHIFT ",TRANS_VBLANK_END_SHIFT },
	{" TRANS_VBLANK_START_SHIFT ",TRANS_VBLANK_START_SHIFT },
	{NULL, 0},
};

struct registers struct__TRANS_VSYNC_A[]={
	{" TRANS_VSYNC_END_SHIFT ",TRANS_VSYNC_END_SHIFT },
	{" TRANS_VSYNC_START_SHIFT ",TRANS_VSYNC_START_SHIFT },
	{NULL, 0},
};

struct registers struct__TRANS_VSYNCSHIFT_A[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DATA_M1[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DATA_N1[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DATA_M2[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DATA_N2[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DP_LINK_M1[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DP_LINK_N1[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DP_LINK_M2[]={
	{NULL, 0},
};

struct registers struct__TRANSA_DP_LINK_N2[]={
	{NULL, 0},
};

struct registers struct__VIDEO_DIP_CTL_A[]={
	{NULL, 0},
};

struct registers struct__VIDEO_DIP_DATA_A[]={
	{NULL, 0},
};

struct registers struct__VIDEO_DIP_GCP_A[]={
	{NULL, 0},
};

struct registers struct__VIDEO_DIP_CTL_B[]={
	{NULL, 0},
};

struct registers struct__VIDEO_DIP_DATA_B[]={
	{NULL, 0},
};

struct registers struct__VIDEO_DIP_GCP_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_HTOTAL_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_HBLANK_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_HSYNC_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_VTOTAL_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_VBLANK_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_VSYNC_B[]={
	{NULL, 0},
};

struct registers struct__TRANS_VSYNCSHIFT_B[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DATA_M1[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DATA_N1[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DATA_M2[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DATA_N2[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DP_LINK_M1[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DP_LINK_N1[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DP_LINK_M2[]={
	{NULL, 0},
};

struct registers struct__TRANSB_DP_LINK_N2[]={
	{NULL, 0},
};

struct registers struct__TRANSACONF[]={
	{NULL, 0},
};

struct registers struct__TRANSBCONF[]={
	{" TRANS_DISABLE ",TRANS_DISABLE },
	{" TRANS_ENABLE ",TRANS_ENABLE },
	{" TRANS_STATE_MASK ",TRANS_STATE_MASK },
	{" TRANS_STATE_DISABLE ",TRANS_STATE_DISABLE },
	{" TRANS_STATE_ENABLE ",TRANS_STATE_ENABLE },
	{" TRANS_FSYNC_DELAY_HB1 ",TRANS_FSYNC_DELAY_HB1 },
	{" TRANS_FSYNC_DELAY_HB2 ",TRANS_FSYNC_DELAY_HB2 },
	{" TRANS_FSYNC_DELAY_HB3 ",TRANS_FSYNC_DELAY_HB3 },
	{" TRANS_FSYNC_DELAY_HB4 ",TRANS_FSYNC_DELAY_HB4 },
	{" TRANS_DP_AUDIO_ONLY ",TRANS_DP_AUDIO_ONLY },
	{" TRANS_DP_VIDEO_AUDIO ",TRANS_DP_VIDEO_AUDIO },
	{" TRANS_INTERLACE_MASK ",TRANS_INTERLACE_MASK },
	{" TRANS_PROGRESSIVE ",TRANS_PROGRESSIVE },
	{" TRANS_INTERLACED ",TRANS_INTERLACED },
	{" TRANS_LEGACY_INTERLACED_ILK ",TRANS_LEGACY_INTERLACED_ILK },
	{" TRANS_8BPC ",TRANS_8BPC },
	{" TRANS_10BPC ",TRANS_10BPC },
	{" TRANS_6BPC ",TRANS_6BPC },
	{" TRANS_12BPC ",TRANS_12BPC },
	{NULL, 0},
};

struct registers struct__TRANSA_CHICKEN2[]={
	{NULL, 0},
};

struct registers struct__TRANSB_CHICKEN2[]={

	{NULL, 0},
};

struct registers struct_SOUTH_CHICKEN1[]={
	{" FDIA_PHASE_SYNC_SHIFT_OVR ",FDIA_PHASE_SYNC_SHIFT_OVR },
	{" FDIA_PHASE_SYNC_SHIFT_EN ",FDIA_PHASE_SYNC_SHIFT_EN },
	{NULL, 0},
};

struct registers struct_SOUTH_CHICKEN2[]={
	{" DPLS_EDP_PPS_FIX_DIS ",DPLS_EDP_PPS_FIX_DIS },
	{NULL, 0},
};

struct registers struct__FDI_RXA_CHICKEN[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_CHICKEN[]={
	{" FDI_RX_PHASE_SYNC_POINTER_OVR ",FDI_RX_PHASE_SYNC_POINTER_OVR },
	{" FDI_RX_PHASE_SYNC_POINTER_EN ",FDI_RX_PHASE_SYNC_POINTER_EN },
	{NULL, 0},
};

struct registers struct_SOUTH_DSPCLK_GATE_D[]={
	{" PCH_DPLSUNIT_CLOCK_GATE_DISABLE ",PCH_DPLSUNIT_CLOCK_GATE_DISABLE },
	{NULL, 0},
};

struct registers struct__FDI_TXA_CTL[]={
	{NULL, 0},
};

struct registers struct__FDI_TXB_CTL[]={
	{" FDI_TX_DISABLE ",FDI_TX_DISABLE },
	{" FDI_TX_ENABLE ",FDI_TX_ENABLE },
	{" FDI_LINK_TRAIN_PATTERN_1 ",FDI_LINK_TRAIN_PATTERN_1 },
	{" FDI_LINK_TRAIN_PATTERN_2 ",FDI_LINK_TRAIN_PATTERN_2 },
	{" FDI_LINK_TRAIN_PATTERN_IDLE ",FDI_LINK_TRAIN_PATTERN_IDLE },
	{" FDI_LINK_TRAIN_NONE ",FDI_LINK_TRAIN_NONE },
	{" FDI_LINK_TRAIN_VOLTAGE_0_4V ",FDI_LINK_TRAIN_VOLTAGE_0_4V },
	{" FDI_LINK_TRAIN_VOLTAGE_0_6V ",FDI_LINK_TRAIN_VOLTAGE_0_6V },
	{" FDI_LINK_TRAIN_VOLTAGE_0_8V ",FDI_LINK_TRAIN_VOLTAGE_0_8V },
	{" FDI_LINK_TRAIN_VOLTAGE_1_2V ",FDI_LINK_TRAIN_VOLTAGE_1_2V },
	{" FDI_LINK_TRAIN_PRE_EMPHASIS_NONE ",FDI_LINK_TRAIN_PRE_EMPHASIS_NONE },
	{" FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X ",FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X },
	{" FDI_LINK_TRAIN_PRE_EMPHASIS_2X ",FDI_LINK_TRAIN_PRE_EMPHASIS_2X },
	{" FDI_LINK_TRAIN_PRE_EMPHASIS_3X ",FDI_LINK_TRAIN_PRE_EMPHASIS_3X },
	{" FDI_DP_PORT_WIDTH_X1 ",FDI_DP_PORT_WIDTH_X1 },
	{" FDI_DP_PORT_WIDTH_X2 ",FDI_DP_PORT_WIDTH_X2 },
	{" FDI_DP_PORT_WIDTH_X3 ",FDI_DP_PORT_WIDTH_X3 },
	{" FDI_DP_PORT_WIDTH_X4 ",FDI_DP_PORT_WIDTH_X4 },
	{" FDI_TX_ENHANCE_FRAME_ENABLE ",FDI_TX_ENHANCE_FRAME_ENABLE },
	{" FDI_TX_PLL_ENABLE ",FDI_TX_PLL_ENABLE },
	{" FDI_LINK_TRAIN_PATTERN_1_IVB ",FDI_LINK_TRAIN_PATTERN_1_IVB },
	{" FDI_LINK_TRAIN_PATTERN_2_IVB ",FDI_LINK_TRAIN_PATTERN_2_IVB },
	{" FDI_LINK_TRAIN_PATTERN_IDLE_IVB ",FDI_LINK_TRAIN_PATTERN_IDLE_IVB },
	{" FDI_LINK_TRAIN_NONE_IVB ",FDI_LINK_TRAIN_NONE_IVB },
	{" FDI_COMPOSITE_SYNC ",FDI_COMPOSITE_SYNC },
	{" FDI_LINK_TRAIN_AUTO ",FDI_LINK_TRAIN_AUTO },
	{" FDI_SCRAMBLING_ENABLE ",FDI_SCRAMBLING_ENABLE },
	{" FDI_SCRAMBLING_DISABLE ",FDI_SCRAMBLING_DISABLE },
	{NULL, 0},
};

struct registers struct__FDI_RXA_CTL[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_CTL[]={
	{" FDI_RX_ENABLE ",FDI_RX_ENABLE },
	{" FDI_FS_ERRC_ENABLE ",FDI_FS_ERRC_ENABLE },
	{" FDI_FE_ERRC_ENABLE ",FDI_FE_ERRC_ENABLE },
	{" FDI_DP_PORT_WIDTH_X8 ",FDI_DP_PORT_WIDTH_X8 },
	{" FDI_8BPC ",FDI_8BPC },
	{" FDI_10BPC ",FDI_10BPC },
	{" FDI_6BPC ",FDI_6BPC },
	{" FDI_12BPC ",FDI_12BPC },
	{" FDI_LINK_REVERSE_OVERWRITE ",FDI_LINK_REVERSE_OVERWRITE },
	{" FDI_DMI_LINK_REVERSE_MASK ",FDI_DMI_LINK_REVERSE_MASK },
	{" FDI_RX_PLL_ENABLE ",FDI_RX_PLL_ENABLE },
	{" FDI_FS_ERR_CORRECT_ENABLE ",FDI_FS_ERR_CORRECT_ENABLE },
	{" FDI_FE_ERR_CORRECT_ENABLE ",FDI_FE_ERR_CORRECT_ENABLE },
	{" FDI_FS_ERR_REPORT_ENABLE ",FDI_FS_ERR_REPORT_ENABLE },
	{" FDI_FE_ERR_REPORT_ENABLE ",FDI_FE_ERR_REPORT_ENABLE },
	{" FDI_RX_ENHANCE_FRAME_ENABLE ",FDI_RX_ENHANCE_FRAME_ENABLE },
	{" FDI_PCDCLK ",FDI_PCDCLK },
	{" FDI_AUTO_TRAINING ",FDI_AUTO_TRAINING },
	{" FDI_LINK_TRAIN_PATTERN_1_CPT ",FDI_LINK_TRAIN_PATTERN_1_CPT },
	{" FDI_LINK_TRAIN_PATTERN_2_CPT ",FDI_LINK_TRAIN_PATTERN_2_CPT },
	{" FDI_LINK_TRAIN_PATTERN_IDLE_CPT ",FDI_LINK_TRAIN_PATTERN_IDLE_CPT },
	{" FDI_LINK_TRAIN_NORMAL_CPT ",FDI_LINK_TRAIN_NORMAL_CPT },
	{" FDI_LINK_TRAIN_PATTERN_MASK_CPT ",FDI_LINK_TRAIN_PATTERN_MASK_CPT },
	{NULL, 0},
};

struct registers struct__FDI_RXA_MISC[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_MISC[]={
	{NULL, 0},
};

struct registers struct__FDI_RXA_TUSIZE1[]={
	{NULL, 0},
};

struct registers struct__FDI_RXA_TUSIZE2[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_TUSIZE1[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_TUSIZE2[]={
	{" FDI_RX_INTER_LANE_ALIGN ",FDI_RX_INTER_LANE_ALIGN },
	{" FDI_RX_TRAIN_PATTERN_2_FAIL ",FDI_RX_TRAIN_PATTERN_2_FAIL },
	{" FDI_RX_FS_CODE_ERR ",FDI_RX_FS_CODE_ERR },
	{" FDI_RX_FE_CODE_ERR ",FDI_RX_FE_CODE_ERR },
	{" FDI_RX_SYMBOL_ERR_RATE_ABOVE ",FDI_RX_SYMBOL_ERR_RATE_ABOVE },
	{" FDI_RX_HDCP_LINK_FAIL ",FDI_RX_HDCP_LINK_FAIL },
	{" FDI_RX_PIXEL_FIFO_OVERFLOW ",FDI_RX_PIXEL_FIFO_OVERFLOW },
	{" FDI_RX_CROSS_CLOCK_OVERFLOW ",FDI_RX_CROSS_CLOCK_OVERFLOW },
	{" FDI_RX_SYMBOL_QUEUE_OVERFLOW ",FDI_RX_SYMBOL_QUEUE_OVERFLOW },
	{NULL, 0},
};

struct registers struct__FDI_RXA_IIR[]={
	{NULL, 0},
};

struct registers struct__FDI_RXA_IMR[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_IIR[]={
	{NULL, 0},
};

struct registers struct__FDI_RXB_IMR[]={
	{NULL, 0},
};

struct registers struct_FDI_PLL_CTL_1[]={
	{NULL, 0},
};

struct registers struct_FDI_PLL_CTL_2[]={
	{NULL, 0},
};

struct registers struct_PCH_ADPA[]={



	{" ADPA_CRT_HOTPLUG_MONITOR_NONE ",ADPA_CRT_HOTPLUG_MONITOR_NONE },
	{" ADPA_CRT_HOTPLUG_MONITOR_MASK ",ADPA_CRT_HOTPLUG_MONITOR_MASK },
	{" ADPA_CRT_HOTPLUG_MONITOR_COLOR ",ADPA_CRT_HOTPLUG_MONITOR_COLOR },
	{" ADPA_CRT_HOTPLUG_MONITOR_MONO ",ADPA_CRT_HOTPLUG_MONITOR_MONO },
	{" ADPA_CRT_HOTPLUG_ENABLE ",ADPA_CRT_HOTPLUG_ENABLE },
	{" ADPA_CRT_HOTPLUG_PERIOD_64 ",ADPA_CRT_HOTPLUG_PERIOD_64 },
	{" ADPA_CRT_HOTPLUG_PERIOD_128 ",ADPA_CRT_HOTPLUG_PERIOD_128 },
	{" ADPA_CRT_HOTPLUG_WARMUP_5MS ",ADPA_CRT_HOTPLUG_WARMUP_5MS },
	{" ADPA_CRT_HOTPLUG_WARMUP_10MS ",ADPA_CRT_HOTPLUG_WARMUP_10MS },
	{" ADPA_CRT_HOTPLUG_SAMPLE_2S ",ADPA_CRT_HOTPLUG_SAMPLE_2S },
	{" ADPA_CRT_HOTPLUG_SAMPLE_4S ",ADPA_CRT_HOTPLUG_SAMPLE_4S },
	{" ADPA_CRT_HOTPLUG_VOLTAGE_40 ",ADPA_CRT_HOTPLUG_VOLTAGE_40 },
	{" ADPA_CRT_HOTPLUG_VOLTAGE_50 ",ADPA_CRT_HOTPLUG_VOLTAGE_50 },
	{" ADPA_CRT_HOTPLUG_VOLTAGE_60 ",ADPA_CRT_HOTPLUG_VOLTAGE_60 },
	{" ADPA_CRT_HOTPLUG_VOLTAGE_70 ",ADPA_CRT_HOTPLUG_VOLTAGE_70 },
	{" ADPA_CRT_HOTPLUG_VOLREF_325MV ",ADPA_CRT_HOTPLUG_VOLREF_325MV },
	{" ADPA_CRT_HOTPLUG_VOLREF_475MV ",ADPA_CRT_HOTPLUG_VOLREF_475MV },
	{" ADPA_CRT_HOTPLUG_FORCE_TRIGGER ",ADPA_CRT_HOTPLUG_FORCE_TRIGGER },
	{NULL, 0},
};

struct registers struct_HDMIB[]={
	{" PORT_ENABLE ",PORT_ENABLE },
	{" TRANSCODER_MASK ",TRANSCODER_MASK },
	{" TRANSCODER_MASK_CPT ",TRANSCODER_MASK_CPT },
	{" COLOR_FORMAT_8bpc ",COLOR_FORMAT_8bpc },
	{" COLOR_FORMAT_12bpc ",COLOR_FORMAT_12bpc },
	{" SDVOB_HOTPLUG_ENABLE ",SDVOB_HOTPLUG_ENABLE },
	{" SDVO_ENCODING ",SDVO_ENCODING },
	{" TMDS_ENCODING ",TMDS_ENCODING },
	{" NULL_PACKET_VSYNC_ENABLE ",NULL_PACKET_VSYNC_ENABLE },
	{" HDMI_MODE_SELECT ",HDMI_MODE_SELECT },
	{" DVI_MODE_SELECT ",DVI_MODE_SELECT },
	{" SDVOB_BORDER_ENABLE ",SDVOB_BORDER_ENABLE },
	{" AUDIO_ENABLE ",AUDIO_ENABLE },
	{" VSYNC_ACTIVE_HIGH ",VSYNC_ACTIVE_HIGH },
	{" HSYNC_ACTIVE_HIGH ",HSYNC_ACTIVE_HIGH },
	{" PORT_DETECTED ",PORT_DETECTED },
	{" PCH_SDVOB ",PCH_SDVOB },
	{NULL, 0},
};

struct registers struct_HDMIC[]={
	{NULL, 0},
};

struct registers struct_HDMID[]={
	{NULL, 0},
};

struct registers struct_BLC_PWM_CPU_CTL2[]={



	{NULL, 0},
};

struct registers struct_BLC_PWM_CPU_CTL[]={
	{NULL, 0},
};

struct registers struct_BLC_PWM_PCH_CTL1[]={





	{NULL, 0},
};

struct registers struct_BLC_PWM_PCH_CTL2[]={
	{NULL, 0},
};

struct registers struct_PCH_PP_STATUS[]={
	{ "PP_ON ", PP_ON},
	{" PP_READY ",PP_READY },
	{" PP_SEQUENCE_NONE ",PP_SEQUENCE_NONE },
	{" PP_SEQUENCE_POWER_UP ",PP_SEQUENCE_POWER_UP },
	{" PP_SEQUENCE_POWER_DOWN ",PP_SEQUENCE_POWER_DOWN },
	{" PP_CYCLE_DELAY_ACTIVE ",PP_CYCLE_DELAY_ACTIVE },
	{" /*undocbit3*/8 ",8 },
	{" /*undocbit2*/4 ",4 },
	{" /*undocbit1*/2 ",2 },
	{" /*undocbit0*/1 ",1 },
	{NULL, 0},
};

struct registers struct_PCH_PP_CONTROL[]={
	{"PCH_PP_UNLOCK", 0xabcd0000},
	{" EDP_FORCE_VDD ",EDP_FORCE_VDD },
	{" EDP_BLC_ENABLE ",EDP_BLC_ENABLE },
	{" PANEL_POWER_RESET ",PANEL_POWER_RESET },
	{" PANEL_POWER_OFF ",PANEL_POWER_OFF },
	{" PANEL_POWER_ON ",PANEL_POWER_ON },
	{NULL, 0},
};

struct registers struct_PCH_PP_ON_DELAYS[]={
	{" PANEL_PORT_SELECT_LVDS ",PANEL_PORT_SELECT_LVDS, PANEL_PORT_SELECT_MASK },
	{" PANEL_PORT_SELECT_DPA ",PANEL_PORT_SELECT_DPA, PANEL_PORT_SELECT_MASK },
	{" EDP_PANEL ",EDP_PANEL, PANEL_PORT_SELECT_MASK },
	{" PANEL_PORT_SELECT_DPC ",PANEL_PORT_SELECT_DPC, PANEL_PORT_SELECT_MASK },
	{" PANEL_PORT_SELECT_DPD ",PANEL_PORT_SELECT_DPD, PANEL_PORT_SELECT_MASK },
	{" PANEL_POWER_UP_DELAY_MASK ", PANEL_POWER_UP_DELAY_MASK, 0xffffffff, 1, PANEL_POWER_UP_DELAY_SHIFT },
	{" PANEL_LIGHT_ON_DELAY_MASK ",PANEL_LIGHT_ON_DELAY_MASK, 0xffffffff, 1, PANEL_LIGHT_ON_DELAY_SHIFT },
	{NULL, 0},
};

struct registers struct_PCH_PP_OFF_DELAYS[]={
	{" PANEL_POWER_DOWN_DELAY_MASK ",PANEL_POWER_DOWN_DELAY_MASK, 0xffffffff, 1, PANEL_POWER_DOWN_DELAY_SHIFT },
	{" PANEL_LIGHT_OFF_DELAY_MASK ",PANEL_LIGHT_OFF_DELAY_MASK, 0xffffffff, 1, PANEL_LIGHT_OFF_DELAY_SHIFT },
	{NULL, 0},
};

struct registers struct_PCH_PP_DIVISOR[]={
	{" PP_REFERENCE_DIVIDER_SHIFT ",PP_REFERENCE_DIVIDER_SHIFT },
	{" PANEL_POWER_CYCLE_DELAY_SHIFT ",PANEL_POWER_CYCLE_DELAY_SHIFT },
	{NULL, 0},
};

struct registers struct_PCH_DP_B[]={
	{NULL, 0},
};

struct registers struct_PCH_DPB_AUX_CH_CTL[]={
	{NULL, 0},
};

struct registers struct_PCH_DPB_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_PCH_DPB_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_PCH_DPB_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_PCH_DPB_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_PCH_DPB_AUX_CH_DATA5[]={
	{NULL, 0},
};

struct registers struct_PCH_DP_C[]={
	{NULL, 0},
};

struct registers struct_PCH_DPC_AUX_CH_CTL[]={
	{NULL, 0},
};

struct registers struct_PCH_DPC_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_PCH_DPC_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_PCH_DPC_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_PCH_DPC_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_PCH_DPC_AUX_CH_DATA5[]={
	{NULL, 0},
};

struct registers struct_PCH_DP_D[]={
	{NULL, 0},
};

struct registers struct_PCH_DPD_AUX_CH_CTL[]={
	{NULL, 0},
};

struct registers struct_PCH_DPD_AUX_CH_DATA1[]={
	{NULL, 0},
};

struct registers struct_PCH_DPD_AUX_CH_DATA2[]={
	{NULL, 0},
};

struct registers struct_PCH_DPD_AUX_CH_DATA3[]={
	{NULL, 0},
};

struct registers struct_PCH_DPD_AUX_CH_DATA4[]={
	{NULL, 0},
};

struct registers struct_PCH_DPD_AUX_CH_DATA5[]={
	{" PORT_TRANS_A_SEL_CPT ",PORT_TRANS_A_SEL_CPT },
	{" PORT_TRANS_B_SEL_CPT ",PORT_TRANS_B_SEL_CPT },
	{" PORT_TRANS_C_SEL_CPT ",PORT_TRANS_C_SEL_CPT },
	{" PORT_TRANS_SEL_MASK ",PORT_TRANS_SEL_MASK },
	{NULL, 0},
};

struct registers struct_TRANS_DP_CTL_A[]={
	{NULL, 0},
};

struct registers struct_TRANS_DP_CTL_B[]={
	{NULL, 0},
};

struct registers struct_TRANS_DP_CTL_C[]={
	{" TRANS_DP_OUTPUT_ENABLE ",TRANS_DP_OUTPUT_ENABLE },
	{" TRANS_DP_PORT_SEL_B ",TRANS_DP_PORT_SEL_B },
	{" TRANS_DP_PORT_SEL_C ",TRANS_DP_PORT_SEL_C },
	{" TRANS_DP_PORT_SEL_D ",TRANS_DP_PORT_SEL_D },
	{" TRANS_DP_PORT_SEL_NONE ",TRANS_DP_PORT_SEL_NONE },
	{" TRANS_DP_PORT_SEL_MASK ",TRANS_DP_PORT_SEL_MASK },
	{" TRANS_DP_AUDIO_ONLY ",TRANS_DP_AUDIO_ONLY },
	{" TRANS_DP_ENH_FRAMING ",TRANS_DP_ENH_FRAMING },
	{" TRANS_DP_8BPC ",TRANS_DP_8BPC },
	{" TRANS_DP_10BPC ",TRANS_DP_10BPC },
	{" TRANS_DP_6BPC ",TRANS_DP_6BPC },
	{" TRANS_DP_12BPC ",TRANS_DP_12BPC },
	{" TRANS_DP_BPC_MASK ",TRANS_DP_BPC_MASK },
	{" TRANS_DP_VSYNC_ACTIVE_HIGH ",TRANS_DP_VSYNC_ACTIVE_HIGH },
	{" TRANS_DP_VSYNC_ACTIVE_LOW ",TRANS_DP_VSYNC_ACTIVE_LOW },
	{" TRANS_DP_HSYNC_ACTIVE_HIGH ",TRANS_DP_HSYNC_ACTIVE_HIGH },
	{" TRANS_DP_HSYNC_ACTIVE_LOW ",TRANS_DP_HSYNC_ACTIVE_LOW },
	{" TRANS_DP_SYNC_MASK ",TRANS_DP_SYNC_MASK },
	{" FORCEWAKE_MT_ENABLE ",FORCEWAKE_MT_ENABLE },
	{" GT_FIFO_CPU_ERROR_MASK ",GT_FIFO_CPU_ERROR_MASK },
	{" GT_FIFO_OVFERR ",GT_FIFO_OVFERR },
	{" GT_FIFO_IAWRERR ",GT_FIFO_IAWRERR },
	{" GT_FIFO_IARDERR ",GT_FIFO_IARDERR },
	{" GT_FIFO_NUM_RESERVED_ENTRIES ",GT_FIFO_NUM_RESERVED_ENTRIES },
	{" GEN6_TURBO_DISABLE ",GEN6_TURBO_DISABLE },
	{" GEN6_AGGRESSIVE_TURBO ",GEN6_AGGRESSIVE_TURBO },
	{" GEN6_RC_CTL_RC6pp_ENABLE ",GEN6_RC_CTL_RC6pp_ENABLE },
	{" GEN6_RC_CTL_RC6p_ENABLE ",GEN6_RC_CTL_RC6p_ENABLE },
	{" GEN6_RC_CTL_RC6_ENABLE ",GEN6_RC_CTL_RC6_ENABLE },
	{" GEN6_RC_CTL_RC1e_ENABLE ",GEN6_RC_CTL_RC1e_ENABLE },
	{" GEN6_RC_CTL_RC7_ENABLE ",GEN6_RC_CTL_RC7_ENABLE },
	{" GEN6_RC_CTL_HW_ENABLE ",GEN6_RC_CTL_HW_ENABLE },
	{" GEN6_CAGF_SHIFT ",GEN6_CAGF_SHIFT },
	{" GEN6_RP_MEDIA_TURBO ",GEN6_RP_MEDIA_TURBO },
	{" GEN6_RP_MEDIA_MODE_MASK ",GEN6_RP_MEDIA_MODE_MASK },
	{" GEN6_RP_MEDIA_HW_TURBO_MODE ",GEN6_RP_MEDIA_HW_TURBO_MODE },
	{" GEN6_RP_MEDIA_HW_NORMAL_MODE ",GEN6_RP_MEDIA_HW_NORMAL_MODE },
	{" GEN6_RP_MEDIA_HW_MODE ",GEN6_RP_MEDIA_HW_MODE },
	{" GEN6_RP_MEDIA_SW_MODE ",GEN6_RP_MEDIA_SW_MODE },
	{" GEN6_RP_MEDIA_IS_GFX ",GEN6_RP_MEDIA_IS_GFX },
	{" GEN6_RP_ENABLE ",GEN6_RP_ENABLE },
	{NULL, 0},
};

struct registers struct_GEN6_PMISR[]={
	{NULL, 0},
};

struct registers struct_GEN6_PMIMR[]={
	{NULL, 0},
};

struct registers struct_GEN6_PMIIR[]={
	{NULL, 0},
};

struct registers struct_GEN6_PMIER[]={
	{" GEN6_PM_MBOX_EVENT ",GEN6_PM_MBOX_EVENT },
	{" GEN6_PM_THERMAL_EVENT ",GEN6_PM_THERMAL_EVENT },
	{" GEN6_PM_RP_DOWN_TIMEOUT ",GEN6_PM_RP_DOWN_TIMEOUT },
	{" GEN6_PM_RP_UP_THRESHOLD ",GEN6_PM_RP_UP_THRESHOLD },
	{" GEN6_PM_RP_DOWN_THRESHOLD ",GEN6_PM_RP_DOWN_THRESHOLD },
	{" GEN6_PM_RP_UP_EI_EXPIRED ",GEN6_PM_RP_UP_EI_EXPIRED },
	{" GEN6_PM_RP_DOWN_EI_EXPIRED ",GEN6_PM_RP_DOWN_EI_EXPIRED },
	{" GEN6_PM_DEFERRED_EVENTS ",GEN6_PM_DEFERRED_EVENTS },
	{" GEN6_PCODE_READY ",GEN6_PCODE_READY },
	{" GEN6_PCODE_FREQ_IA_RATIO_SHIFT ",GEN6_PCODE_FREQ_IA_RATIO_SHIFT },
	{" GEN6_CORE_CPD_STATE_MASK ",GEN6_CORE_CPD_STATE_MASK },
	{" GEN6_RC0 ",GEN6_RC0 },
	{" GEN6_RC3 ",GEN6_RC3 },
	{" GEN6_RC6 ",GEN6_RC6 },
	{" GEN6_RC7 ",GEN6_RC7 },
	{NULL, 0},
};

struct registers struct_G4X_AUD_VID_DID[]={
	{NULL, 0},
};

struct registers struct_G4X_AUD_CNTL_ST[]={
	{" G4X_ELDV_DEVCL_DEVBLC ",G4X_ELDV_DEVCL_DEVBLC },
	{" G4X_ELDV_DEVCTG ",G4X_ELDV_DEVCTG },
	{" G4X_ELD_ACK ",G4X_ELD_ACK },
	{NULL, 0},
};

struct registers struct_G4X_HDMIW_HDMIEDID[]={
	{NULL, 0},
};

struct registers struct_IBX_HDMIW_HDMIEDID_A[]={
	{NULL, 0},
};

struct registers struct_IBX_AUD_CNTL_ST_A[]={
	{" IBX_ELD_ACK ",IBX_ELD_ACK },
	{NULL, 0},
};

struct registers struct_IBX_AUD_CNTL_ST2[]={
	{" IBX_ELD_VALIDB ",IBX_ELD_VALIDB },
	{" IBX_CP_READYB ",IBX_CP_READYB },
	{NULL, 0},
};

struct registers struct_CPT_HDMIW_HDMIEDID_A[]={
	{NULL, 0},
};

struct registers struct_CPT_AUD_CNTL_ST_A[]={
	{NULL, 0},
};

struct registers struct_CPT_AUD_CNTRL_ST2[]={
	{NULL, 0},
};

struct registers struct_IBX_AUD_CONFIG_A[]={
	{NULL, 0},
};

struct registers struct_CPT_AUD_CONFIG_A[]={
	{" AUD_CONFIG_N_VALUE_INDEX ",AUD_CONFIG_N_VALUE_INDEX },
	{" AUD_CONFIG_N_PROG_ENABLE ",AUD_CONFIG_N_PROG_ENABLE },
	{" AUD_CONFIG_UPPER_N_SHIFT ",AUD_CONFIG_UPPER_N_SHIFT },
	{" AUD_CONFIG_LOWER_N_SHIFT ",AUD_CONFIG_LOWER_N_SHIFT },
	{" AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT ",AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT },
	{" AUD_CONFIG_DISABLE_NCTS ",AUD_CONFIG_DISABLE_NCTS },
};

struct registers *reglist[] = {
	[C0DRB3] = (struct registers *)struct_C0DRB3,
	[C1DRB3] = (struct registers *)struct_C1DRB3,
	[ECOSKPD] = (struct registers *)struct_ECOSKPD,
	[CLKCFG] = (struct registers *)struct_CLKCFG,
	[GEN6_BLITTER_HWSTAM] = (struct registers *)struct_GEN6_BLITTER_HWSTAM,
	[_VIDEO_DIP_GCP_A] = (struct registers *)struct__VIDEO_DIP_GCP_A,
	[TSC1] = (struct registers *)struct_TSC1,
	[GEN6_BLITTER_IMR] = (struct registers *)struct_GEN6_BLITTER_IMR,
	[_VIDEO_DIP_CTL_B] = (struct registers *)struct__VIDEO_DIP_CTL_B,
	[PCH_GPIOC] = (struct registers *)struct_PCH_GPIOC,
	[TR1] = (struct registers *)struct_TR1,
	[GEN6_BLITTER_ECOSKPD] = (struct registers *)struct_GEN6_BLITTER_ECOSKPD,
	[_VIDEO_DIP_DATA_B] = (struct registers *)struct__VIDEO_DIP_DATA_B,
	[PCH_GPIOD] = (struct registers *)struct_PCH_GPIOD,
	[_PIPEB_DATA_M1] = (struct registers *)struct__PIPEB_DATA_M1,
	[TSFS] = (struct registers *)struct_TSFS,
	[_VIDEO_DIP_GCP_B] = (struct registers *)struct__VIDEO_DIP_GCP_B,
	[PCH_GPIOE] = (struct registers *)struct_PCH_GPIOE,
	[_PIPEB_DATA_N1] = (struct registers *)struct__PIPEB_DATA_N1,
	[CRSTANDVID] = (struct registers *)struct_CRSTANDVID,
	[GEN6_BSD_HWSTAM] = (struct registers *)struct_GEN6_BSD_HWSTAM,
	[_TRANS_HTOTAL_B] = (struct registers *)struct__TRANS_HTOTAL_B,
	[PCH_GPIOF] = (struct registers *)struct_PCH_GPIOF,
	[_PIPEB_DATA_M2] = (struct registers *)struct__PIPEB_DATA_M2,
	[PXVFREQ_BASE] = (struct registers *)struct_PXVFREQ_BASE,
	[GEN6_BSD_IMR] = (struct registers *)struct_GEN6_BSD_IMR,
	[_TRANS_HBLANK_B] = (struct registers *)struct__TRANS_HBLANK_B,
	[PCH_GMBUS0] = (struct registers *)struct_PCH_GMBUS0,
	[_PIPEB_DATA_N2] = (struct registers *)struct__PIPEB_DATA_N2,
	[VIDFREQ_BASE] = (struct registers *)struct_VIDFREQ_BASE,
	[GEN6_BSD_RNCID] = (struct registers *)struct_GEN6_BSD_RNCID,
	[_TRANS_HSYNC_B] = (struct registers *)struct__TRANS_HSYNC_B,
	[PCH_GMBUS1] = (struct registers *)struct_PCH_GMBUS1,
	[_PIPEB_LINK_M1] = (struct registers *)struct__PIPEB_LINK_M1,
	[VIDFREQ1] = (struct registers *)struct_VIDFREQ1,
	[FBC_CFB_BASE] = (struct registers *)struct_FBC_CFB_BASE,
	[_TRANS_VTOTAL_B] = (struct registers *)struct__TRANS_VTOTAL_B,
	[PCH_GMBUS2] = (struct registers *)struct_PCH_GMBUS2,
	[_PIPEB_LINK_N1] = (struct registers *)struct__PIPEB_LINK_N1,
	[FBC_LL_BASE] = (struct registers *)struct_FBC_LL_BASE,
	[_TRANS_VBLANK_B] = (struct registers *)struct__TRANS_VBLANK_B,
	[PCH_GMBUS3] = (struct registers *)struct_PCH_GMBUS3,
	[_PIPEB_LINK_M2] = (struct registers *)struct__PIPEB_LINK_M2,
	[_TRANS_VSYNC_B] = (struct registers *)struct__TRANS_VSYNC_B,
	[PCH_GMBUS4] = (struct registers *)struct_PCH_GMBUS4,
	[_PIPEB_LINK_N2] = (struct registers *)struct__PIPEB_LINK_N2,
	[PCH_GMBUS5] = (struct registers *)struct_PCH_GMBUS5,
	[_PFA_CTL_1] = (struct registers *)struct__PFA_CTL_1,
	[_PFB_CTL_1] = (struct registers *)struct__PFB_CTL_1,
	[IPEIR_I965] = (struct registers *)struct_IPEIR_I965,
	[IPEHR_I965] = (struct registers *)struct_IPEHR_I965,
	[INSTDONE_I965] = (struct registers *)struct_INSTDONE_I965,
	[INSTPS] = (struct registers *)struct_INSTPS,
	[INSTDONE1] = (struct registers *)struct_INSTDONE1,
	[ACTHD_I965] = (struct registers *)struct_ACTHD_I965,
	[_SPRB_KEYVAL] = (struct registers *)struct__SPRB_KEYVAL,
	[_SPRB_KEYMSK] = (struct registers *)struct__SPRB_KEYMSK,
	[_DVSAPOS] = (struct registers *)struct__DVSAPOS,
	[_SPRB_SURF] = (struct registers *)struct__SPRB_SURF,
	[_DVSASIZE] = (struct registers *)struct__DVSASIZE,
	[_CURBCNTR_IVB] = (struct registers *)struct__CURBCNTR_IVB,
	[_SPRB_KEYMAX] = (struct registers *)struct__SPRB_KEYMAX,
	[_DVSAKEYVAL] = (struct registers *)struct__DVSAKEYVAL,
	[_CURBBASE_IVB] = (struct registers *)struct__CURBBASE_IVB,
	[_SPRB_TILEOFF] = (struct registers *)struct__SPRB_TILEOFF,
	[_DVSAKEYMSK] = (struct registers *)struct__DVSAKEYMSK,
	[_CURBPOS_IVB] = (struct registers *)struct__CURBPOS_IVB,
	[_SPRB_SCALE] = (struct registers *)struct__SPRB_SCALE,
	[_DVSASURF] = (struct registers *)struct__DVSASURF,
	[_DSPACNTR] = (struct registers *)struct__DSPACNTR,
	[_SPRB_GAMC] = (struct registers *)struct__SPRB_GAMC,
	[_DVSAKEYMAXVAL] = (struct registers *)struct__DVSAKEYMAXVAL,
	[_DSPAADDR] = (struct registers *)struct__DSPAADDR,
	[VGACNTRL] = (struct registers *)struct_VGACNTRL,
	[_DVSATILEOFF] = (struct registers *)struct__DVSATILEOFF,
	[_DSPASTRIDE] = (struct registers *)struct__DSPASTRIDE,
	[CPU_VGACNTRL] = (struct registers *)struct_CPU_VGACNTRL,
	[_DVSASURFLIVE] = (struct registers *)struct__DVSASURFLIVE,
	[_DSPAPOS] = (struct registers *)struct__DSPAPOS,
	[DIGITAL_PORT_HOTPLUG_CNTRL] = (struct registers *)struct_DIGITAL_PORT_HOTPLUG_CNTRL,
	[_DVSASCALE] = (struct registers *)struct__DVSASCALE,
	[_DSPASIZE] = (struct registers *)struct__DSPASIZE,
	[_DVSAGAMC] = (struct registers *)struct__DVSAGAMC,
	[_DSPASURF] = (struct registers *)struct__DSPASURF,
	[_DSPATILEOFF] = (struct registers *)struct__DSPATILEOFF,
	[_PIPEB_DP_LINK_N] = (struct registers *)struct__PIPEB_DP_LINK_N,
	[_PIPEADSL] = (struct registers *)struct__PIPEADSL,
	[TV_H_CHROMA_59] = (struct registers *)struct_TV_H_CHROMA_59,
	[_PIPEACONF] = (struct registers *)struct__PIPEACONF,
	[TV_V_LUMA_0] = (struct registers *)struct_TV_V_LUMA_0,
	[_PIPEASTAT] = (struct registers *)struct__PIPEASTAT,
	[TV_V_LUMA_42] = (struct registers *)struct_TV_V_LUMA_42,
	[DSPARB] = (struct registers *)struct_DSPARB,
	[TV_V_CHROMA_0] = (struct registers *)struct_TV_V_CHROMA_0,
	[DSPFW1] = (struct registers *)struct_DSPFW1,
	[TV_V_CHROMA_42] = (struct registers *)struct_TV_V_CHROMA_42,
	[DSPFW2] = (struct registers *)struct_DSPFW2,
	[DP_A] = (struct registers *)struct_DP_D,
	[DSPFW3] = (struct registers *)struct_DSPFW3,
	[DP_B] = (struct registers *)struct_DP_D,
	[WM0_PIPEA_ILK] = (struct registers *)struct_WM0_PIPEA_ILK,
	[DP_C] = (struct registers *)struct_DP_D,
	[WM0_PIPEB_ILK] = (struct registers *)struct_WM0_PIPEB_ILK,
	[DP_D] = (struct registers *)struct_DP_D,
	[DPA_AUX_CH_CTL] = (struct registers *)struct_DPA_AUX_CH_CTL,
	[TRANS_DP_CTL_B] = (struct registers *)struct_TRANS_DP_CTL_B,
	[_PIPEASRC] = (struct registers *)struct__PIPEASRC,
	[TRANS_DP_CTL_C] = (struct registers *)struct_TRANS_DP_CTL_C,
	[_FDI_RXB_IIR] = (struct registers *)struct__FDI_RXB_IIR,
	[_BCLRPAT_A] = (struct registers *)struct__BCLRPAT_A,
	[DEW] = (struct registers *)struct_DEW,
	[GEN6_PMISR] = (struct registers *)struct_GEN6_PMISR,
	[_FDI_RXB_IMR] = (struct registers *)struct__FDI_RXB_IMR,
	[_VSYNCSHIFT_A] = (struct registers *)struct__VSYNCSHIFT_A,
	[MCHAFE] = (struct registers *)struct_MCHAFE,
	[GEN6_PMIMR] = (struct registers *)struct_GEN6_PMIMR,
	[FDI_PLL_CTL_1] = (struct registers *)struct_FDI_PLL_CTL_1,
	[_HTOTAL_B] = (struct registers *)struct__HTOTAL_B,
	[CSIEC] = (struct registers *)struct_CSIEC,
	[GEN6_PMIIR] = (struct registers *)struct_GEN6_PMIIR,
	[FDI_PLL_CTL_2] = (struct registers *)struct_FDI_PLL_CTL_2,
	[_HBLANK_B] = (struct registers *)struct__HBLANK_B,
	[DMIEC] = (struct registers *)struct_DMIEC,
	[GEN6_PMIER] = (struct registers *)struct_GEN6_PMIER,
	[PCH_ADPA] = (struct registers *)struct_PCH_ADPA,
	[_HSYNC_B] = (struct registers *)struct__HSYNC_B,
	[DDREC] = (struct registers *)struct_DDREC,
	[G4X_AUD_VID_DID] = (struct registers *)struct_G4X_AUD_VID_DID,
	[HDMIB] = (struct registers *)struct_HDMIB,
	[_VTOTAL_B] = (struct registers *)struct__VTOTAL_B,
	[PEG0EC] = (struct registers *)struct_PEG0EC,
	[G4X_AUD_CNTL_ST] = (struct registers *)struct_G4X_AUD_CNTL_ST,
	[HDMIC] = (struct registers *)struct_HDMIC,
	[_VBLANK_B] = (struct registers *)struct__VBLANK_B,
	[PEG1EC] = (struct registers *)struct_PEG1EC,
	[G4X_HDMIW_HDMIEDID] = (struct registers *)struct_G4X_HDMIW_HDMIEDID,
	[HDMID] = (struct registers *)struct_HDMID,
	[_VSYNC_B] = (struct registers *)struct__VSYNC_B,
	[GFXEC] = (struct registers *)struct_GFXEC,
	[IBX_HDMIW_HDMIEDID_A] = (struct registers *)struct_IBX_HDMIW_HDMIEDID_A,
	[_PIPEBSRC] = (struct registers *)struct__PIPEBSRC,
	[RPPREVBSYTUPAVG] = (struct registers *)struct_RPPREVBSYTUPAVG,
	[BLC_PWM_CPU_CTL2] = (struct registers *)struct_BLC_PWM_CPU_CTL2,
	[RPPREVBSYTDNAVG] = (struct registers *)struct_RPPREVBSYTDNAVG,
	[VIDFREQ2] = (struct registers *)struct_VIDFREQ2,
	[VIDFREQ3] = (struct registers *)struct_VIDFREQ3,
	[FBC_CONTROL] = (struct registers *)struct_FBC_CONTROL,
	[VIDFREQ4] = (struct registers *)struct_VIDFREQ4,
	[FBC_COMMAND] = (struct registers *)struct_FBC_COMMAND,
	[HWS_PGA] = (struct registers *)struct_HWS_PGA,
	[INTTOEXT_BASE_ILK] = (struct registers *)struct_INTTOEXT_BASE_ILK,
	[FBC_STATUS] = (struct registers *)struct_FBC_STATUS,
	[IPEIR] = (struct registers *)struct_IPEIR,
	[_PCH_DPLL_A] = (struct registers *)struct__PCH_DPLL_A,
	[INTTOEXT_BASE] = (struct registers *)struct_INTTOEXT_BASE,
	[FBC_CONTROL2] = (struct registers *)struct_FBC_CONTROL2,
	[IPEHR] = (struct registers *)struct_IPEHR,
	[_PCH_DPLL_B] = (struct registers *)struct__PCH_DPLL_B,
	[_PFA_WIN_SZ] = (struct registers *)struct__PFA_WIN_SZ,
	[MEMSWCTL] = (struct registers *)struct_MEMSWCTL,
	[FBC_FENCE_OFF] = (struct registers *)struct_FBC_FENCE_OFF,
	[INSTDONE] = (struct registers *)struct_INSTDONE,
	[_PCH_FPA0] = (struct registers *)struct__PCH_FPA0,
	[_PFB_WIN_SZ] = (struct registers *)struct__PFB_WIN_SZ,
	[MEMIHYST] = (struct registers *)struct_MEMIHYST,
	[FBC_TAG] = (struct registers *)struct_FBC_TAG,
	[NOPID] = (struct registers *)struct_NOPID,
	[_PCH_FPA1] = (struct registers *)struct__PCH_FPA1,
	[_PFA_WIN_POS] = (struct registers *)struct__PFA_WIN_POS,
	[MEMINTREN] = (struct registers *)struct_MEMINTREN,
	[ILK_DPFC_CB_BASE] = (struct registers *)struct_ILK_DPFC_CB_BASE,
	[HWSTAM] = (struct registers *)struct_HWSTAM,
	[_PCH_FPB0] = (struct registers *)struct__PCH_FPB0,
	[_PFB_WIN_POS] = (struct registers *)struct__PFB_WIN_POS,
	[MEMINTRSTR] = (struct registers *)struct_MEMINTRSTR,
	[ILK_DPFC_CONTROL] = (struct registers *)struct_ILK_DPFC_CONTROL,
	[ERROR_GEN6] = (struct registers *)struct_ERROR_GEN6,
	[_PCH_FPB1] = (struct registers *)struct__PCH_FPB1,
	[_PFA_VSCALE] = (struct registers *)struct__PFA_VSCALE,
	[MEMINTRSTS] = (struct registers *)struct_MEMINTRSTS,
	[ILK_DPFC_RECOMP_CTL] = (struct registers *)struct_ILK_DPFC_RECOMP_CTL,
	[_3D_CHICKEN] = (struct registers *)struct__3D_CHICKEN,
	[PCH_DPLL_TEST] = (struct registers *)struct_PCH_DPLL_TEST,
	[_PFB_VSCALE] = (struct registers *)struct__PFB_VSCALE,
	[ILK_DPFC_STATUS] = (struct registers *)struct_ILK_DPFC_STATUS,
	[_3D_CHICKEN2] = (struct registers *)struct__3D_CHICKEN2,
	[PCH_DREF_CONTROL] = (struct registers *)struct_PCH_DREF_CONTROL,
	[_PFA_HSCALE] = (struct registers *)struct__PFA_HSCALE,
	[_3D_CHICKEN3] = (struct registers *)struct__3D_CHICKEN3,
	[PCH_RAWCLK_FREQ] = (struct registers *)struct_PCH_RAWCLK_FREQ,
	[_PFB_HSCALE] = (struct registers *)struct__PFB_HSCALE,
	[PCH_DPLL_TMR_CFG] = (struct registers *)struct_PCH_DPLL_TMR_CFG,
	[_LGC_PALETTE_A] = (struct registers *)struct__LGC_PALETTE_A,
	[_LGC_PALETTE_B] = (struct registers *)struct__LGC_PALETTE_B,
	[RR_HW_CTL] = (struct registers *)struct_RR_HW_CTL,
	[FDI_PLL_BIOS_0] = (struct registers *)struct_FDI_PLL_BIOS_0,
	[_DVSBCNTR] = (struct registers *)struct__DVSBCNTR,
	[FDI_PLL_BIOS_1] = (struct registers *)struct_FDI_PLL_BIOS_1,
	[SWF00] = (struct registers *)struct_SWF00,
	[_DVSBLINOFF] = (struct registers *)struct__DVSBLINOFF,
	[FDI_PLL_BIOS_2] = (struct registers *)struct_FDI_PLL_BIOS_2,
	[SWF01] = (struct registers *)struct_SWF01,
	[_DVSBSTRIDE] = (struct registers *)struct__DVSBSTRIDE,
	[DISPLAY_PORT_PLL_BIOS_0] = (struct registers *)struct_DISPLAY_PORT_PLL_BIOS_0,
	[SWF02] = (struct registers *)struct_SWF02,
	[_DVSBPOS] = (struct registers *)struct__DVSBPOS,
	[DISPLAY_PORT_PLL_BIOS_1] = (struct registers *)struct_DISPLAY_PORT_PLL_BIOS_1,
	[SWF03] = (struct registers *)struct_SWF03,
	[_DVSBSIZE] = (struct registers *)struct__DVSBSIZE,
	[DISPLAY_PORT_PLL_BIOS_2] = (struct registers *)struct_DISPLAY_PORT_PLL_BIOS_2,
	[SWF04] = (struct registers *)struct_SWF04,
	[_DVSBKEYVAL] = (struct registers *)struct__DVSBKEYVAL,

	[SWF05] = (struct registers *)struct_SWF05,
	[_DVSBKEYMSK] = (struct registers *)struct__DVSBKEYMSK,
	[PCH_3DCGDIS0] = (struct registers *)struct_PCH_3DCGDIS0,
	[SWF06] = (struct registers *)struct_SWF06,
	[_DVSBSURF] = (struct registers *)struct__DVSBSURF,
	[PCH_3DCGDIS1] = (struct registers *)struct_PCH_3DCGDIS1,
	[SWF10] = (struct registers *)struct_SWF10,
	[_DVSBKEYMAXVAL] = (struct registers *)struct__DVSBKEYMAXVAL,
	[SWF11] = (struct registers *)struct_SWF11,
	[_DVSBTILEOFF] = (struct registers *)struct__DVSBTILEOFF,
	[SWF14] = (struct registers *)struct_SWF14,
	[WM0_PIPEC_IVB] = (struct registers *)struct_WM0_PIPEC_IVB,
	[WM1_LP_ILK] = (struct registers *)struct_WM1_LP_ILK,
	[DPA_AUX_CH_DATA1] = (struct registers *)struct_DPA_AUX_CH_DATA1,
	[WM2_LP_ILK] = (struct registers *)struct_WM1_LP_ILK,
	[DPA_AUX_CH_DATA2] = (struct registers *)struct_DPA_AUX_CH_DATA2,
	[TV_CSC_Y2] = (struct registers *)struct_TV_CSC_Y2,
	[WM3_LP_ILK] = (struct registers *)struct_WM1_LP_ILK,
	[DPA_AUX_CH_DATA3] = (struct registers *)struct_DPA_AUX_CH_DATA3,
	[TV_CSC_U] = (struct registers *)struct_TV_CSC_U,
	[WM1S_LP_ILK] = (struct registers *)struct_WM1S_LP_ILK,
	[DPA_AUX_CH_DATA4] = (struct registers *)struct_DPA_AUX_CH_DATA4,
	[TV_CSC_U2] = (struct registers *)struct_TV_CSC_U2,
	[WM2S_LP_IVB] = (struct registers *)struct_WM2S_LP_IVB,
	[DPA_AUX_CH_DATA5] = (struct registers *)struct_DPA_AUX_CH_DATA5,
	[TV_CSC_V] = (struct registers *)struct_TV_CSC_V,
	[WM3S_LP_IVB] = (struct registers *)struct_WM3S_LP_IVB,
	[DPB_AUX_CH_CTL] = (struct registers *)struct_DPB_AUX_CH_CTL,
	[TV_CSC_V2] = (struct registers *)struct_TV_CSC_V2,
	[MLTR_ILK] = (struct registers *)struct_MLTR_ILK,
	[DPB_AUX_CH_DATA1] = (struct registers *)struct_DPB_AUX_CH_DATA1,
	[TV_CLR_KNOBS] = (struct registers *)struct_TV_CLR_KNOBS,
	[_PIPEAFRAMEHIGH] = (struct registers *)struct__PIPEAFRAMEHIGH,
	[DPB_AUX_CH_DATA2] = (struct registers *)struct_DPB_AUX_CH_DATA2,
	[TV_CLR_LEVEL] = (struct registers *)struct_TV_CLR_LEVEL,
	[_PIPEAFRAMEPIXEL] = (struct registers *)struct__PIPEAFRAMEPIXEL,
	[DPB_AUX_CH_DATA3] = (struct registers *)struct_DPB_AUX_CH_DATA3,
	[TV_H_CTL_1] = (struct registers *)struct_TV_H_CTL_1,
	[DPB_AUX_CH_DATA4] = (struct registers *)struct_DPB_AUX_CH_DATA4,
	[TV_H_CTL_2] = (struct registers *)struct_TV_H_CTL_2,
	[TV_H_CTL_3] = (struct registers *)struct_TV_H_CTL_3,
	[IBX_AUD_CNTL_ST_A] = (struct registers *)struct_IBX_AUD_CNTL_ST_A,
	[_BCLRPAT_B] = (struct registers *)struct__BCLRPAT_B,
	[IBX_AUD_CNTL_ST2] = (struct registers *)struct_IBX_AUD_CNTL_ST2,
	[BLC_PWM_CPU_CTL] = (struct registers *)struct_BLC_PWM_CPU_CTL,
	[_VSYNCSHIFT_B] = (struct registers *)struct__VSYNCSHIFT_B,
	[ECR] = (struct registers *)struct_ECR,
	[CPT_HDMIW_HDMIEDID_A] = (struct registers *)struct_CPT_HDMIW_HDMIEDID_A,
	[BLC_PWM_PCH_CTL1] = (struct registers *)struct_BLC_PWM_PCH_CTL1,
	[_TRANS_VSYNCSHIFT_B] = (struct registers *)struct__TRANS_VSYNCSHIFT_B,
	[ADPA] = (struct registers *)struct_ADPA,
	[OGW0] = (struct registers *)struct_OGW0,
	[CPT_AUD_CNTL_ST_A] = (struct registers *)struct_CPT_AUD_CNTL_ST_A,
	[BLC_PWM_PCH_CTL2] = (struct registers *)struct_BLC_PWM_PCH_CTL2,
	[_TRANSB_DATA_M1] = (struct registers *)struct__TRANSB_DATA_M1,
	[PORT_HOTPLUG_EN] = (struct registers *)struct_PORT_HOTPLUG_EN,
	[OGW1] = (struct registers *)struct_OGW1,
	[CPT_AUD_CNTRL_ST2] = (struct registers *)struct_CPT_AUD_CNTRL_ST2,
	[PCH_PP_STATUS] = (struct registers *)struct_PCH_PP_STATUS,
	[_TRANSB_DATA_N1] = (struct registers *)struct__TRANSB_DATA_N1,
	[PORT_HOTPLUG_STAT] = (struct registers *)struct_PORT_HOTPLUG_STAT,
	[EG0] = (struct registers *)struct_EG0,
	[IBX_AUD_CONFIG_A] = (struct registers *)struct_IBX_AUD_CONFIG_A,
	[PCH_PP_CONTROL] = (struct registers *)struct_PCH_PP_CONTROL,
	[_TRANSB_DATA_M2] = (struct registers *)struct__TRANSB_DATA_M2,
	[SDVOB] = (struct registers *)struct_SDVOB,
	[EG1] = (struct registers *)struct_EG1,
	[CPT_AUD_CONFIG_A] = (struct registers *)struct_CPT_AUD_CONFIG_A,
	[PCH_PP_ON_DELAYS] = (struct registers *)struct_PCH_PP_ON_DELAYS,
	[_TRANSB_DATA_N2] = (struct registers *)struct__TRANSB_DATA_N2,
	[SDVOC] = (struct registers *)struct_SDVOC,
	[EG2] = (struct registers *)struct_EG2,
	[PCH_PP_OFF_DELAYS] = (struct registers *)struct_PCH_PP_OFF_DELAYS,
	[_TRANSB_DP_LINK_M1] = (struct registers *)struct__TRANSB_DP_LINK_M1,
	[EG3] = (struct registers *)struct_EG3,
	[PCH_PP_DIVISOR] = (struct registers *)struct_PCH_PP_DIVISOR,
	[_TRANSB_DP_LINK_N1] = (struct registers *)struct__TRANSB_DP_LINK_N1,
	[DVOB] = (struct registers *)struct_DVOB,
	[EG4] = (struct registers *)struct_EG4,
	[PCH_DP_B] = (struct registers *)struct_PCH_DP_B,
	[_TRANSB_DP_LINK_M2] = (struct registers *)struct__TRANSB_DP_LINK_M2,
	[EG5] = (struct registers *)struct_EG5,
	[PCH_DPB_AUX_CH_CTL] = (struct registers *)struct_PCH_DPB_AUX_CH_CTL,
	[_TRANSB_DP_LINK_N2] = (struct registers *)struct__TRANSB_DP_LINK_N2,
	[EG6] = (struct registers *)struct_EG6,
	[_TRANSACONF] = (struct registers *)struct__TRANSACONF,
	[ILK_DPFC_FENCE_YOFF] = (struct registers *)struct_ILK_DPFC_FENCE_YOFF,
	[ILK_DPFC_CHICKEN] = (struct registers *)struct_ILK_DPFC_CHICKEN,
	[MI_MODE] = (struct registers *)struct_MI_MODE,
	[ILK_DISPLAY_CHICKEN1] = (struct registers *)struct_ILK_DISPLAY_CHICKEN1,
	[GFX_MODE] = (struct registers *)struct_GFX_MODE,
	[PCH_SSC4_PARMS] = (struct registers *)struct_PCH_SSC4_PARMS,
	[_DPLL_A] = (struct registers *)struct__DPLL_A,
	[GFX_MODE_GEN7] = (struct registers *)struct_GFX_MODE_GEN7,
	[PCH_SSC4_AUX_PARMS] = (struct registers *)struct_PCH_SSC4_AUX_PARMS,
	[DEISR] = (struct registers *)struct_DEISR,
	[_DPLL_B] = (struct registers *)struct__DPLL_B,
	[SCPD0] = (struct registers *)struct_SCPD0,
	[PCH_DPLL_SEL] = (struct registers *)struct_PCH_DPLL_SEL,
	[DEIMR] = (struct registers *)struct_DEIMR,
	[PPCR] = (struct registers *)struct_PPCR,
	[IER] = (struct registers *)struct_IER,
	[_TRANS_HTOTAL_A] = (struct registers *)struct__TRANS_HTOTAL_A,
	[DEIIR] = (struct registers *)struct_DEIIR,
	[DVOB] = (struct registers *)struct_DVOB,
	[IIR] = (struct registers *)struct_IIR,
	[_TRANS_HBLANK_A] = (struct registers *)struct__TRANS_HBLANK_A,
	[DEIER] = (struct registers *)struct_DEIER,
	[DVOC] = (struct registers *)struct_DVOC,
	[IMR] = (struct registers *)struct_IMR,
	[_TRANS_HSYNC_A] = (struct registers *)struct__TRANS_HSYNC_A,
	[GTISR] = (struct registers *)struct_GTISR,
	[LVDS] = (struct registers *)struct_LVDS,
	[ISR] = (struct registers *)struct_ISR,
	[_TRANS_VTOTAL_A] = (struct registers *)struct__TRANS_VTOTAL_A,
	[GTIMR] = (struct registers *)struct_GTIMR,
	[_DPLL_A_MD] = (struct registers *)struct__DPLL_A_MD,
	[EIR] = (struct registers *)struct_EIR,
	[_TRANS_VBLANK_A] = (struct registers *)struct__TRANS_VBLANK_A,
	[GTIIR] = (struct registers *)struct_GTIIR,
	[EMR] = (struct registers *)struct_EMR,
	[_TRANS_VSYNC_A] = (struct registers *)struct__TRANS_VSYNC_A,
	[GTIER] = (struct registers *)struct_GTIER,
	[_TRANS_VSYNCSHIFT_A] = (struct registers *)struct__TRANS_VSYNCSHIFT_A,
	[ILK_DISPLAY_CHICKEN2] = (struct registers *)struct_ILK_DISPLAY_CHICKEN2,
	[ILK_DISPLAY_CHICKEN_FUSES] = (struct registers *)struct_ILK_DISPLAY_CHICKEN_FUSES,
	[_DVSBSURFLIVE] = (struct registers *)struct__DVSBSURFLIVE,
	[_DVSBSCALE] = (struct registers *)struct__DVSBSCALE,
	[SWF30] = (struct registers *)struct_SWF30,
	[_DVSBGAMC] = (struct registers *)struct__DVSBGAMC,
	[SWF31] = (struct registers *)struct_SWF31,
	[_SPRA_CTL] = (struct registers *)struct__SPRA_CTL,
	[SWF32] = (struct registers *)struct_SWF32,
	[_SPRA_LINOFF] = (struct registers *)struct__SPRA_LINOFF,
	[_PIPEBDSL] = (struct registers *)struct__PIPEBDSL,
	[_SPRA_STRIDE] = (struct registers *)struct__SPRA_STRIDE,
	[_PIPEBCONF] = (struct registers *)struct__PIPEBCONF,
	[_SPRA_POS] = (struct registers *)struct__SPRA_POS,
	[_PIPEBSTAT] = (struct registers *)struct__PIPEBSTAT,
	[_SPRA_SIZE] = (struct registers *)struct__SPRA_SIZE,
	[_PIPEBFRAMEHIGH] = (struct registers *)struct__PIPEBFRAMEHIGH,
	[_SPRA_KEYVAL] = (struct registers *)struct__SPRA_KEYVAL,
	[_PIPEBFRAMEPIXEL] = (struct registers *)struct__PIPEBFRAMEPIXEL,
	[_SPRA_KEYMSK] = (struct registers *)struct__SPRA_KEYMSK,
	[_PIPEB_FRMCOUNT_GM45] = (struct registers *)struct__PIPEB_FRMCOUNT_GM45,
	[_PIPEB_FLIPCOUNT_GM45] = (struct registers *)struct__PIPEB_FLIPCOUNT_GM45,
	[_PIPEA_FRMCOUNT_GM45] = (struct registers *)struct__PIPEA_FRMCOUNT_GM45,
	[_PIPEA_FLIPCOUNT_GM45] = (struct registers *)struct__PIPEA_FLIPCOUNT_GM45,
	[DPB_AUX_CH_DATA5] = (struct registers *)struct_DPB_AUX_CH_DATA5,
	[_CURACNTR] = (struct registers *)struct__CURACNTR,
	[DPC_AUX_CH_CTL] = (struct registers *)struct_DPC_AUX_CH_CTL,
	[TV_V_CTL_1] = (struct registers *)struct_TV_V_CTL_1,
	[_CURABASE] = (struct registers *)struct__CURABASE,
	[DPC_AUX_CH_DATA1] = (struct registers *)struct_DPC_AUX_CH_DATA1,
	[TV_V_CTL_2] = (struct registers *)struct_TV_V_CTL_2,
	[_CURAPOS] = (struct registers *)struct__CURAPOS,
	[DPC_AUX_CH_DATA2] = (struct registers *)struct_DPC_AUX_CH_DATA2,
	[TV_V_CTL_3] = (struct registers *)struct_TV_V_CTL_3,
	[CURSOR_POS_MASK] = (struct registers *)struct_CURSOR_POS_MASK,
	[DPC_AUX_CH_DATA3] = (struct registers *)struct_DPC_AUX_CH_DATA3,
	[TV_V_CTL_4] = (struct registers *)struct_TV_V_CTL_4,
	[CURSIZE] = (struct registers *)struct_CURSIZE,
	[DPC_AUX_CH_DATA4] = (struct registers *)struct_DPC_AUX_CH_DATA4,
	[TV_V_CTL_5] = (struct registers *)struct_TV_V_CTL_5,
	[_CURBCNTR] = (struct registers *)struct__CURBCNTR,
	[DPC_AUX_CH_DATA5] = (struct registers *)struct_DPC_AUX_CH_DATA5,
	[TV_V_CTL_6] = (struct registers *)struct_TV_V_CTL_6,
	[_CURBBASE] = (struct registers *)struct__CURBBASE,
	[DPD_AUX_CH_CTL] = (struct registers *)struct_DPD_AUX_CH_CTL,
	[TV_V_CTL_7] = (struct registers *)struct_TV_V_CTL_7,
	[_CURBPOS] = (struct registers *)struct__CURBPOS,
	[DPD_AUX_CH_DATA1] = (struct registers *)struct_DPD_AUX_CH_DATA1,
	[TV_SC_CTL_1] = (struct registers *)struct_TV_SC_CTL_1,
	[DPD_AUX_CH_DATA2] = (struct registers *)struct_DPD_AUX_CH_DATA2,
	[TV_SC_CTL_2] = (struct registers *)struct_TV_SC_CTL_2,
	[TV_SC_CTL_3] = (struct registers *)struct_TV_SC_CTL_3,
	[DVOA_SRCDIM] = (struct registers *)struct_DVOA_SRCDIM,
	[PCH_DPB_AUX_CH_DATA1] = (struct registers *)struct_PCH_DPB_AUX_CH_DATA1,
	[DVOB_SRCDIM] = (struct registers *)struct_DVOB_SRCDIM,
	[EG7] = (struct registers *)struct_EG7,
	[PCH_DPB_AUX_CH_DATA2] = (struct registers *)struct_PCH_DPB_AUX_CH_DATA2,
	[_TRANSBCONF] = (struct registers *)struct__TRANSBCONF,
	[DVOC_SRCDIM] = (struct registers *)struct_DVOC_SRCDIM,
	[PXW] = (struct registers *)struct_PXW,
	[MEMMODECTL] = (struct registers *)struct_MEMMODECTL,
	[PCH_DPB_AUX_CH_DATA3] = (struct registers *)struct_PCH_DPB_AUX_CH_DATA3,
	[_TRANSA_CHICKEN2] = (struct registers *)struct__TRANSA_CHICKEN2,
	[PXWL] = (struct registers *)struct_PXWL,
	[RCBMAXAVG] = (struct registers *)struct_RCBMAXAVG,
	[PCH_DPB_AUX_CH_DATA4] = (struct registers *)struct_PCH_DPB_AUX_CH_DATA4,
	[_TRANSB_CHICKEN2] = (struct registers *)struct__TRANSB_CHICKEN2,
	[VIDEO_DIP_DATA] = (struct registers *)struct_VIDEO_DIP_DATA,
	[LCFUSE02] = (struct registers *)struct_LCFUSE02,
	[MEMSWCTL2] = (struct registers *)struct_MEMSWCTL2,
	[PCH_DPB_AUX_CH_DATA5] = (struct registers *)struct_PCH_DPB_AUX_CH_DATA5,
	[SOUTH_CHICKEN1] = (struct registers *)struct_SOUTH_CHICKEN1,
	[VIDEO_DIP_CTL] = (struct registers *)struct_VIDEO_DIP_CTL,
	[CSIPLL0] = (struct registers *)struct_CSIPLL0,
	[MEMSTAT_CTG] = (struct registers *)struct_MEMSTAT_CTG,
	[PCH_DP_C] = (struct registers *)struct_PCH_DP_C,
	[SOUTH_CHICKEN2] = (struct registers *)struct_SOUTH_CHICKEN2,
	[PP_STATUS] = (struct registers *)struct_PP_STATUS,
	[PEG_BAND_GAP_DATA] = (struct registers *)struct_PEG_BAND_GAP_DATA,
	[RCBMINAVG] = (struct registers *)struct_RCBMINAVG,
	[PCH_DPC_AUX_CH_CTL] = (struct registers *)struct_PCH_DPC_AUX_CH_CTL,
	[_FDI_RXA_CHICKEN] = (struct registers *)struct__FDI_RXA_CHICKEN,
	[PP_CONTROL] = (struct registers *)struct_PP_CONTROL,
	[OVADD] = (struct registers *)struct_OVADD,
	[RCUPEI] = (struct registers *)struct_RCUPEI,
	[PCH_DPC_AUX_CH_DATA1] = (struct registers *)struct_PCH_DPC_AUX_CH_DATA1,
	[_FDI_RXB_CHICKEN] = (struct registers *)struct__FDI_RXB_CHICKEN,
	[PP_ON_DELAYS] = (struct registers *)struct_PP_ON_DELAYS,
	[DOVSTA] = (struct registers *)struct_DOVSTA,
	[RCDNEI] = (struct registers *)struct_RCDNEI,
	[PCH_DPC_AUX_CH_DATA2] = (struct registers *)struct_PCH_DPC_AUX_CH_DATA2,
	[SOUTH_DSPCLK_GATE_D] = (struct registers *)struct_SOUTH_DSPCLK_GATE_D,
	[PP_OFF_DELAYS] = (struct registers *)struct_PP_OFF_DELAYS,
	[OGAMC5] = (struct registers *)struct_OGAMC5,
	[RSTDBYCTL] = (struct registers *)struct_RSTDBYCTL,
	[PCH_DPC_AUX_CH_DATA3] = (struct registers *)struct_PCH_DPC_AUX_CH_DATA3,
	[_FDI_TXA_CTL] = (struct registers *)struct__FDI_TXA_CTL,
	[OGAMC4] = (struct registers *)struct_OGAMC4,
	[VIDCTL] = (struct registers *)struct_VIDCTL,
	[_FDI_TXB_CTL] = (struct registers *)struct__FDI_TXB_CTL,
	[VIDSTS] = (struct registers *)struct_VIDSTS,
	[_DPLL_B_MD] = (struct registers *)struct__DPLL_B_MD,
	[_FPA0] = (struct registers *)struct__FPA0,
	[ESR] = (struct registers *)struct_ESR,
	[_FPA1] = (struct registers *)struct__FPA1,
	[INSTPM] = (struct registers *)struct_INSTPM,
	[_TRANSA_DATA_M1] = (struct registers *)struct__TRANSA_DATA_M1,
	[_FPB0] = (struct registers *)struct__FPB0,
	[ACTHD] = (struct registers *)struct_ACTHD,
	[_TRANSA_DATA_N1] = (struct registers *)struct__TRANSA_DATA_N1,

	[_FPB1] = (struct registers *)struct__FPB1,
	[FW_BLC] = (struct registers *)struct_FW_BLC,
	[_TRANSA_DATA_M2] = (struct registers *)struct__TRANSA_DATA_M2,
	[IVB_CHICKEN3] = (struct registers *)struct_IVB_CHICKEN3,
	[FDI_PLL_FREQ_CTL] = (struct registers *)struct_FDI_PLL_FREQ_CTL,
	[_PALETTE_A] = (struct registers *)struct__PALETTE_A,
	[FW_BLC2] = (struct registers *)struct_FW_BLC2,
	[_TRANSA_DATA_N2] = (struct registers *)struct__TRANSA_DATA_N2,
	[DISP_ARB_CTL] = (struct registers *)struct_DISP_ARB_CTL,
	[FDI_PLL_FREQ_LOCK_LIMIT_MASK] = (struct registers *)struct_FDI_PLL_FREQ_LOCK_LIMIT_MASK,
	[_PALETTE_B] = (struct registers *)struct__PALETTE_B,
	[FW_BLC_SELF] = (struct registers *)struct_FW_BLC_SELF,
	[_TRANSA_DP_LINK_M1] = (struct registers *)struct__TRANSA_DP_LINK_M1,
	[SDEISR] = (struct registers *)struct_SDEISR,
	[_PIPEA_DATA_M1] = (struct registers *)struct__PIPEA_DATA_M1,
	[MCHBAR_MIRROR_BASE] = (struct registers *)struct_MCHBAR_MIRROR_BASE,
	[MI_ARB_STATE] = (struct registers *)struct_MI_ARB_STATE,
	[_TRANSA_DP_LINK_N1] = (struct registers *)struct__TRANSA_DP_LINK_N1,
	[SDEIMR] = (struct registers *)struct_SDEIMR,
	[_PIPEA_DATA_N1] = (struct registers *)struct__PIPEA_DATA_N1,
	[DCC] = (struct registers *)struct_DCC,

	[_TRANSA_DP_LINK_M2] = (struct registers *)struct__TRANSA_DP_LINK_M2,
	[SDEIIR] = (struct registers *)struct_SDEIIR,
	[_PIPEA_DATA_M2] = (struct registers *)struct__PIPEA_DATA_M2,
	[CSHRDDR3CTL] = (struct registers *)struct_CSHRDDR3CTL,
	[BB_ADDR] = (struct registers *)struct_BB_ADDR,
	[_TRANSA_DP_LINK_N2] = (struct registers *)struct__TRANSA_DP_LINK_N2,
	[SDEIER] = (struct registers *)struct_SDEIER,
	[_PIPEA_DATA_N2] = (struct registers *)struct__PIPEA_DATA_N2,
	[GFX_FLSH_CNTL] = (struct registers *)struct_GFX_FLSH_CNTL,
	[_VIDEO_DIP_CTL_A] = (struct registers *)struct__VIDEO_DIP_CTL_A,
	[PCH_PORT_HOTPLUG] = (struct registers *)struct_PCH_PORT_HOTPLUG,
	[_PIPEA_LINK_M1] = (struct registers *)struct__PIPEA_LINK_M1,
	[_VIDEO_DIP_DATA_A] = (struct registers *)struct__VIDEO_DIP_DATA_A,
	[PCH_GPIOA] = (struct registers *)struct_PCH_GPIOA,
	[_PIPEA_LINK_N1] = (struct registers *)struct__PIPEA_LINK_N1,
	[PCH_GPIOB] = (struct registers *)struct_PCH_GPIOB,
	[_PIPEA_LINK_M2] = (struct registers *)struct__PIPEA_LINK_M2,
	[_PIPEA_LINK_N2] = (struct registers *)struct__PIPEA_LINK_N2,
	[_SPRA_SURF] = (struct registers *)struct__SPRA_SURF,
	[_DSPBCNTR] = (struct registers *)struct__DSPBCNTR,
	[_SPRA_KEYMAX] = (struct registers *)struct__SPRA_KEYMAX,
	[_DSPBADDR] = (struct registers *)struct__DSPBADDR,
	[_SPRA_TILEOFF] = (struct registers *)struct__SPRA_TILEOFF,
	[_DSPBSTRIDE] = (struct registers *)struct__DSPBSTRIDE,
	[_SPRA_SCALE] = (struct registers *)struct__SPRA_SCALE,
	[_DSPBPOS] = (struct registers *)struct__DSPBPOS,
	[_SPRA_GAMC] = (struct registers *)struct__SPRA_GAMC,
	[_DSPBSIZE] = (struct registers *)struct__DSPBSIZE,
	[_SPRB_CTL] = (struct registers *)struct__SPRB_CTL,
	[_DSPBSURF] = (struct registers *)struct__DSPBSURF,
	[_SPRB_LINOFF] = (struct registers *)struct__SPRB_LINOFF,
	[_SPRB_STRIDE] = (struct registers *)struct__SPRB_STRIDE,
	[_DSPBTILEOFF] = (struct registers *)struct__DSPBTILEOFF,
	[_SPRB_POS] = (struct registers *)struct__SPRB_POS,
	[_DVSACNTR] = (struct registers *)struct__DVSACNTR,
	[_SPRB_SIZE] = (struct registers *)struct__SPRB_SIZE,
	[_DVSALINOFF] = (struct registers *)struct__DVSALINOFF,
	[_DVSASTRIDE] = (struct registers *)struct__DVSASTRIDE,
	[DPD_AUX_CH_DATA3] = (struct registers *)struct_DPD_AUX_CH_DATA3,
	[DPD_AUX_CH_DATA4] = (struct registers *)struct_DPD_AUX_CH_DATA4,
	[TV_WIN_POS] = (struct registers *)struct_TV_WIN_POS,
	[DPD_AUX_CH_DATA5] = (struct registers *)struct_DPD_AUX_CH_DATA5,
	[TV_WIN_SIZE] = (struct registers *)struct_TV_WIN_SIZE,
	[_PIPEA_GMCH_DATA_M] = (struct registers *)struct__PIPEA_GMCH_DATA_M,
	[TV_FILTER_CTL_1] = (struct registers *)struct_TV_FILTER_CTL_1,
	[_PIPEB_GMCH_DATA_M] = (struct registers *)struct__PIPEB_GMCH_DATA_M,
	[TV_FILTER_CTL_2] = (struct registers *)struct_TV_FILTER_CTL_2,
	[_PIPEA_GMCH_DATA_N] = (struct registers *)struct__PIPEA_GMCH_DATA_N,
	[TV_FILTER_CTL_3] = (struct registers *)struct_TV_FILTER_CTL_3,
	[_PIPEB_GMCH_DATA_N] = (struct registers *)struct__PIPEB_GMCH_DATA_N,
	[TV_CC_CONTROL] = (struct registers *)struct_TV_CC_CONTROL,
	[_PIPEA_DP_LINK_M] = (struct registers *)struct__PIPEA_DP_LINK_M,
	[TV_CC_DATA] = (struct registers *)struct_TV_CC_DATA,
	[_PIPEB_DP_LINK_M] = (struct registers *)struct__PIPEB_DP_LINK_M,
	[TV_H_LUMA_0] = (struct registers *)struct_TV_H_LUMA_0,
	[_PIPEA_DP_LINK_N] = (struct registers *)struct__PIPEA_DP_LINK_N,
	[TV_H_LUMA_59] = (struct registers *)struct_TV_H_LUMA_59,
	[TV_H_CHROMA_0] = (struct registers *)struct_TV_H_CHROMA_0,
	[PP_DIVISOR] = (struct registers *)struct_PP_DIVISOR,
	[PCH_DPC_AUX_CH_DATA4] = (struct registers *)struct_PCH_DPC_AUX_CH_DATA4,
	[PFIT_CONTROL] = (struct registers *)struct_PFIT_CONTROL,
	[OGAMC3] = (struct registers *)struct_OGAMC3,
	[PCH_DPC_AUX_CH_DATA5] = (struct registers *)struct_PCH_DPC_AUX_CH_DATA5,
	[_FDI_RXA_CTL] = (struct registers *)struct__FDI_RXA_CTL,
	[PFIT_PGM_RATIOS] = (struct registers *)struct_PFIT_PGM_RATIOS,
	[OGAMC2] = (struct registers *)struct_OGAMC2,
	[VIDSTART] = (struct registers *)struct_VIDSTART,
	[PCH_DP_D] = (struct registers *)struct_PCH_DP_D,
	[_FDI_RXB_CTL] = (struct registers *)struct__FDI_RXB_CTL,
	[PFIT_AUTO_RATIOS] = (struct registers *)struct_PFIT_AUTO_RATIOS,
	[OGAMC1] = (struct registers *)struct_OGAMC1,
	[MEMSTAT_ILK] = (struct registers *)struct_MEMSTAT_ILK,
	[PCH_DPD_AUX_CH_CTL] = (struct registers *)struct_PCH_DPD_AUX_CH_CTL,
	[_FDI_RXA_MISC] = (struct registers *)struct__FDI_RXA_MISC,
	[BLC_PWM_CTL] = (struct registers *)struct_BLC_PWM_CTL,
	[OGAMC0] = (struct registers *)struct_OGAMC0,
	[RCPREVBSYTUPAVG] = (struct registers *)struct_RCPREVBSYTUPAVG,
	[PCH_DPD_AUX_CH_DATA1] = (struct registers *)struct_PCH_DPD_AUX_CH_DATA1,
	[_FDI_RXB_MISC] = (struct registers *)struct__FDI_RXB_MISC,
	[BLC_PWM_CTL2] = (struct registers *)struct_BLC_PWM_CTL2,
	[_HTOTAL_A] = (struct registers *)struct__HTOTAL_A,
	[RCPREVBSYTDNAVG] = (struct registers *)struct_RCPREVBSYTDNAVG,
	[PCH_DPD_AUX_CH_DATA2] = (struct registers *)struct_PCH_DPD_AUX_CH_DATA2,
	[_FDI_RXA_TUSIZE1] = (struct registers *)struct__FDI_RXA_TUSIZE1,
	[BLC_HIST_CTL] = (struct registers *)struct_BLC_HIST_CTL,
	[_HBLANK_A] = (struct registers *)struct__HBLANK_A,
	[PMMISC] = (struct registers *)struct_PMMISC,
	[PCH_DPD_AUX_CH_DATA3] = (struct registers *)struct_PCH_DPD_AUX_CH_DATA3,
	[_FDI_RXA_TUSIZE2] = (struct registers *)struct__FDI_RXA_TUSIZE2,
	[TV_CTL] = (struct registers *)struct_TV_CTL,
	[_HSYNC_A] = (struct registers *)struct__HSYNC_A,
	[SDEW] = (struct registers *)struct_SDEW,
	[PCH_DPD_AUX_CH_DATA4] = (struct registers *)struct_PCH_DPD_AUX_CH_DATA4,
	[_FDI_RXB_TUSIZE1] = (struct registers *)struct__FDI_RXB_TUSIZE1,
	[TV_DAC] = (struct registers *)struct_TV_DAC,
	[_VTOTAL_A] = (struct registers *)struct__VTOTAL_A,
	[CSIEW0] = (struct registers *)struct_CSIEW0,
	[PCH_DPD_AUX_CH_DATA5] = (struct registers *)struct_PCH_DPD_AUX_CH_DATA5,
	[_FDI_RXB_TUSIZE2] = (struct registers *)struct__FDI_RXB_TUSIZE2,
	[TV_CSC_Y] = (struct registers *)struct_TV_CSC_Y,
	[_VBLANK_A] = (struct registers *)struct__VBLANK_A,
	[CSIEW1] = (struct registers *)struct_CSIEW1,
	[TRANS_DP_CTL_A] = (struct registers *)struct_TRANS_DP_CTL_A,
	[_FDI_RXA_IIR] = (struct registers *)struct__FDI_RXA_IIR,
	[_VSYNC_A] = (struct registers *)struct__VSYNC_A,
	[CSIEW2] = (struct registers *)struct_CSIEW2,
	[_FDI_RXA_IMR] = (struct registers *)struct__FDI_RXA_IMR,
	[PEW] = (struct registers *)struct_PEW,
	[0x100000] = NULL,
};

